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preliminary data sheet september 2000 ort8850 field-programmable system chip (fpsc) eight-channel x 850 mbits/s backplane transceiver introduction field-programmable system chips (fpscs) bring a whole new dimension to programmable logic: fpga logic and an embedded system solution on a single device. lucent technologies microelectronics group has developed a solution for designers who need the many advantages of fpga-based design implementa- tion, coupled with high-speed serial backplane data transfer. built on the series 4 reconfigurable embed- ded system-on-chips (soc) architecture, the ort8850 family is made up of backplane transceivers containing eight channels, each operating at up to 850 mbits/s (6.8 gbits/s when all eight channels are used) full-duplex synchronous interface with built-in clock and data recovery (cdr) in standard-cell logic, along with up to 600 k usable fpga system gates. the cdr circuitry is a macrocell available from lucent's smart silicon macro library, and has already been implemented in numerous applications including asics, standard products, and fpscs to create inter- faces for sonet/sdh sts-3/stm-1, sts-12/stm-4, sts-48/stm-16, and sts-192/stm-64 applications. with the addition of protocol and access logic such as protocol-independent framers, asynchronous transfer mode (atm) framers, packet-over-sonet (pos) interfaces, and framers for hdlc for internet protocol (ip), designers can build a configurable interface retaining proven backplane driver/receiver technol- ogy. designers can also use the device to drive high- speed data transfer across buses within a system that are not sonet/sdh based. for example, designers can build a 6.8 gbits/s pci-to-pci half bridge using our pci soft core. the ort8850 family offers a clockless high-speed interface for interdevice communication, on a board or across a backplane. the built-in clock recovery of the ort8850 allows for higher system performance, eas- ier-to-design clock domains in a multiboard system, and fewer signals on the backplane. network design- ers will benefit from the backplane transceiver as a network termination device. the backplane trans- ceiver offers sonet scrambling/descrambling of data and streamlined sonet framing, pointer moving and transport overhead handling, plus the programmable logic to terminate the network into proprietary sys- tems. for non-sonet application, all sonet func- tionality is hidden from the user and no prior networking knowledge is required. the 8850 also offers 8b/10b coding in addition to sonet scram- bling. also included on the device are three full-duplex, high- speed parallel interfaces, consisting of 8-bit data, con- trol (such as start-of-cell), and clock. the interface delivers double data rate (ddr) data at rates up to 311 mhz (622 mbits/s per pin), and converts this data internal to the device into 32-bit wide data running at half rate on one clock edge. functions such as center- ing the transmit clock in the transmit data eye are done automatically by the interface. applications deliv- ered by this interface include a parallel backplane interface similar to the recently proposed rapidio * packet-based interface. * rapidio is a trademark of motorola, inc. table 1. orca ort8850 familyavailable fpga logic ? the embedded core and interface are not included in the above gate counts.the usable gate counts range from a logic-only gate count to a gate count assuming 20% of the pfus/slics being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates/pfu), including 12 gates per lut/ff pair (eight per pfu), and 12 gates per slic/ff pair (one per pfu). each of the fo ur pio groups are counted as 16 gates (three ffs, fast-capture latch, output logic, clk, and i/o buffers). pfus used as ram are counte d at four gates per bit, with each pfu capable of implementing a 32 x 4 ram (or 512 gates) per pfu. embedded block ram (ebr) is counted a s four gates per bit plus each block has an additional 25 k gates. 7 k gates are used for each pll and 50k gates for the embedded system bus and microprocessor interface logic. both the ebr and plls are conservatively utilized in the gate calculations. device pfu rows pfu columns total pfus fpga user i/o luts ebr blocks ebr bits (k) usable gates (k) ort8850l 26 24 624 296 4,992 8 74 260470 ort8850h 46 44 2024 536 16,192 16 147 530970
table of contents contents page contents page 2 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc introduction..................................................................1 list of figures ..............................................................2 list of tables ...............................................................3 embedded core features (serial)...............................4 embedded core features (parallel)............................4 programmable fpga features ...................................5 system features .........................................................6 description...................................................................7 what is an fpsc? .....................................................7 fpsc overview ..........................................................7 fpsc gate counting ..................................................7 fpga/embedded core interface ................................7 orca foundry 2000 development system ...............7 fpsc design kit .........................................................8 fpga logic overview ................................................8 plc logic ...................................................................8 programmable i/o ......................................................9 routing .......................................................................9 system level features..............................................10 microprocessor interface ..........................................10 system bus ..............................................................10 phase-locked loops .................................................10 embedded block ram .............................................10 configuration ............................................................11 additional information ...............................................11 ort8850 overview ...................................................12 device layout ...........................................................12 backplane transceiver interface ..............................12 hsi interface .............................................................15 stm macrocell ..........................................................15 8b/10b encoder/decoder .........................................15 fpga interface .........................................................15 byte-wide parallel interface .....................................15 fpsc configuration ..................................................16 generic backplane transceiver application..............17 synchronous transfer mode (stm) .........................17 8b/10b mode ............................................................17 backplane transceiver core detailed description ....18 hsi macro .................................................................18 stm transmitter (fpga -> backplane) ...................20 stm receiver (backplane -> fpga) .......................24 powerdown mode .....................................................31 redundancy and protection switching .....................31 rapidio interface to pi-sched...................................32 overview ...................................................................32 receive cell interface ..............................................32 transmit cell interface .............................................34 memory map..............................................................36 definition of register types .....................................36 memory map overview .............................................38 absolute maximum ratings.......................................52 recommend operating conditions ...........................52 power supply decoupling lc circuit ....................... 53 hsi electrical and timing characteristics ................ 54 embedded core lvds i/o ....................................... 55 lvds receiver buffer requirements ...................... 56 input/output buffer measurement conditions (on-lvds buffer) ...................................................... 57 lvds buffer characteristics..................................... 58 termination resistor ............................................... 58 lvds driver buffer capabilities .............................. 58 pin information ......................................................... 59 package pinouts ...................................................... 72 package thermal characteristics summary ............ 93 q ja .......................................................................... 93 y jc .......................................................................... 93 q jc .......................................................................... 93 q jb .......................................................................... 93 fpsc maximum junction temperature .................. 93 package thermal characteristics............................. 94 package coplanarity ................................................ 94 package parasitics ................................................... 94 package outline diagrams....................................... 95 terms and definitions .............................................. 95 680-pin pbgam ...................................................... 96 hardware ordering information ................................ 97 software ordering information ................................. 97
table of contents contents page contents page 3 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc list of fi g ures figure 1. orca ort8850 block diagram ...............13 figure 2. high level diagram of ort8850 transceiver .............................................................14 figure 3. hsi functional block diagram ..................19 figure 4. byte ordering of input/output interface in sts-12 mode ..........................................................20 figure 5. interconnect of streams for fifo alignment ................................................................25 figure 6. example of intra-stm alignment ..............25 figure 7. example of inter-stm alignment ..............25 figure 8. example of twin sts-12 stream alignment ................................................................25 figure 9. examples of link alignment ......................26 figure 10. pointer mover state machine ..................28 figure 11. spe and c1j1 functionality ....................30 figure 12. spe stuff bytes .......................................31 figure 13. rapidio receive cell interface ...............33 figure 14. rapidio transmit cell interface ..............34 figure 15. sample power supply filter network for analog hsi power supply pins ...............................53 figure 16. ac test loads ..........................................57 figure 17. output buffer delays ...............................57 figure 18. input buffer delays ..................................57 figure 19. lvds driver and receiver and associated internal components ...............................................58 figure 20. lvds driver and receiver ......................58 figure 21. lvds driver ............................................58 figure 22. package parasitics ..................................94 list of tables table 1. orca ort8850 famil y available fpga lo g ic ......................................................................... 1 table 2. transmitter toh on lvds output ( transparent mode ) ................................................ 22 table 3. transmitter toh on lvds output ( toh insert mode ) .................................................. 22 table 4. valid startin g positions for an sts-mc ...... 27 table 5. receiver toh ( output parallel bus ) ........... 29 table 6. spe and c1j1 functionalit y ........................ 30 table 7. rapidio si g nals to/from fpga ................... 35 table 8. si g nals used as re g ister bits .................... 36 table 9. structural re g ister elements ...................... 37 table 10. memor y map ............................................. 38 table 11. memor y map descriptions ........................ 46 table 12. absolute maximum ratin g s ...................... 52 table 13. recommend operatin g conditions ........... 52 table 14. absolute maximum ratin g s ...................... 54 table 15. recommended operatin g conditions ....... 54 table 16. receiver specifications ............................ 54 table 17. transmitter specifications ......................... 54 table 18.s y nthesizer specifications ......................... 54 table 19. driver dc data ........................................... 55 table 20. driver ac data ........................................... 55 table 21. driver power consumption ....................... 55 table 22. receiver ac data ...................................... 56 table 23. receiver power consumption .................. 56 table 24. receiver dc data ...................................... 56 table 25. lvds operatin g parameters .................... 56 table 26. fpga common-function pin description ....................................................... 59 table 27. fpsc function pin description ................ 62 table 28. embedded core/fpga interface si g nal description ................................................... 65 table 29. ort8850h 680-pin pbgam pinout ......... 73 table 30. orca ort8850 plastic packa g e thermal guidelines ................................................. 94 table 31. orca ort8850 packa g e parasitics ....... 94 table 32. device t y pe options ................................. 97 table 33. temperature options ................................ 97 table 34. packa g e t y pe options .............................. 97 table 35. orca fpsc packa g e matrix ( speed grades ) ...................................................... 97
4 4 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc embedded core features (serial) n implemented in an orca series 4 fpga array. n allows wide range of applications for sonet net- work termination application as well as generic data moving for high-speed backplane data transfer. n no knowledge of sonet/sdh needed in generic applications. simply supply data, 78 mhz106 mhz clock, and a frame pulse. n high-speed interface (hsi) function for clock/data recovery serial backplane data transfer without exter- nal clocks. n eight-channel hsi function provides 850 mbits/s serial interface per channel for a total chip bandwidth of 6.8 gbits/s (full duplex). n hsi function uses lucent technologies microelec- tronics group's 850 mbits/s serial interface core. rates from 212 mbits/s to 850 mbits/s are supported directly (lower rates directly supported through deci- mation and interpolation). n lvds i/os compliant with eia *-644 support hot insertion. all embedded lvds i/os include both input and output on-board termination to allow long-haul driving of backplanes. n low-power 1.5 v hsi core. n low-power lvds buffers. n programmable sts-1, sts-3, and sts-12 framing. n independent sts-1, sts-3, and sts-12 data streams per quad channels. n 8:1 data multiplexing/demultiplexing for 106.25 mhz byte-wide data processing in fpga logic. n on-chip, phase-lock loop (pll) clock meets b jitter tolerance specification of itu-t recommendation g.958. n powerdown option of hsi receiver on a per-channel basis. n selectable 8b/10b coder/decoder or sonet scram- bler/descrambler. n hsi automatically recovers from loss-of-clock once its reference clock returns to normal operating state. n frame alignment across multiple ort8850 devices for work/protect switching at oc-192/stm-64 and above rates. n in-band management and configuration through transport overhead extraction/insertion. n supports transparent modes where either the only insertion is a1/a2 framing bytes, or no bytes are inserted. n streamlined pointer processor (pointer mover) for 8 khz frame alignment to system clocks. n built-in boundry scan ( ieee ? 1149.1 jtag). n fifos align incoming data across all eight channels (two groups of four channels or four groups of two channels) for both sonet scrambling and 8b/10b modes. optional ability to bypass alignment fifos. n 1 + 1 protection supports sts-12/sts-48 redun- dancy by either software or hardware control for pro- tection switching applications. sts-192 and above rates are supported through multiple devices. n orca fpga soft intellectual property core support for a variety of applications. n programmable stm pointer mover bypass mode. n programmable stm framer bypass mode. n programmable cdr bypass mode (clocked lvds high-speed interface). n redundant outputs and multiplexed redundant inputs for cdr i/os allow for implementation of eight chan- nels with redundancy on a single device. embedded core features (parallel) n three full-duplex, double data rate (ddr) i/o groups include 8-bit data, one control, and one clock. each interface is implemented with lvds i/os that include on-board termination to allow long-haul driving of backplanes, such as the industry standard rapidio interface. n external i/o speeds on ddr interface up to 311 mhz (622 mbits/s per pin), with internal, single- edge data transferred at 1/2 rate on a 32-bit bus plus control. n automatic centering of transmit clock in data eye for ddr interface. n direct interfaces to lucent pi-sched (266 mhz ddr lvds), pi-x (128 mhz ttl), and apc (100 mhz ttl) atm/ip switch/port controller devices. * eia is a registered trademark of electronic industries association. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc.
lucent technologies inc. 5 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pro g rammable fpga features n hi g h-performance platform desi g n: 0.13 m 7-level metal technology. internal performance of >250 mhz. over 600k usable system gates. meets multiple i/o interface standards. 1.5 v operation (30% less power than 1.8 v oper- ation) translates to greater performance. n traditional i/o selections: lvttl and lvcmos (3.3 v, 2.5 v, and 1.8 v) i/os. per pin-selectable i/o clamping diodes provide 3.3 v pci compliance. individually programmable drive capability: 24 ma sink/12 ma source, 12 ma sink/6 ma source, or 6 ma sink/3 ma source. two slew rates supported (fast and slew-limited). fast-capture input latch and input flip-flop (ff)/latch for reduced input setup time and zero hold time. fast open-drain drive capability. capability to register 3-state enable signal. off-chip clock drive capability. two-input function generator in output path. n new pro g rammable hi g h-speed i/o: single-ended: gtl, gtl+, pecl, sstl3/2 (class i & ii), hstl (class i, iii, iv), zbt, and ddr. double-ended: lvds, bused-lvds, lvpecl. lvds include optional on-chip termination resistor per i/o and on-chip reference generation. customer defined: ability to substitute arbitrary standard cell i/o to meet fast-moving standards. n new capabilit y to ( de ) multiplex i/o si g nals: new ddr on both input and output at rates up to 133 mhz (266 mhz effective rate). new 2x and 4x downlink and uplink capability per i/o (i.e., 50 mhz internal to 200 mhz i/o). n enhanced twin- q uad pro g rammable function unit ( pfu ) : eight 16-bit look-up tables (luts) per pfu. nine user registers per pfu, one following each lut, and organized to allow two nibbles to act independently, plus one extra for arithmetic opera- tions. new register control in each pfu has two inde- pendent programmable clocks, clock enables, local set/reset, and data selects. new lut structure allows flexible combinations of lut4, lut5, new lut6, 4 ? 1 mux, new 8 ? 1 mux, and ripple mode arithmetic functions in the same pfu. 32 x 4 ram per pfu, configurable as single- or dual-port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. soft-wired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu through fast internal routing, which reduces rout- ing congestion and improves speed. flexible fast access to pfu inputs from routing. fast-carry logic and routing to all four adjacent pfus for nibble-wide, byte-wide, or longer arith- metic functions, with the option to register the pfu carry-out. n abundant high-speed buffered and nonbuffered rout- ing resources provide 2x average speed improve- ments over previous architectures. n hierarchical routing optimized for both local and glo- bal routing with dedicated routing resources. this results in faster routing times with predictable and efficient performance. n slic provides eight 3-statable buffers, up to 10-bit decoder, and pa l *-like and-or-invert (aoi) in each programmable logic cell. n improved built-in clock management with dual output programmable phase-locked loops (pplls) provide optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 mhz up to 416 mhz. n new 200 mhz embedded q uad-port ram blocks, 2 read ports, 2 write ports, and 2 sets of b y te lane enables. each embedded ram block can be confi g - ured as: 1512x18 (quad-port, two read/two write) with optional built in arbitration. 1256x36 (dual-port, one read/one write). 11kx9 (dual-port, one read/one write). 2512x9 (dual-port, one read/one write for each). 2 rams with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). supports joining of ram blocks. two 16x8-bit content addressable memory (cam) support. fifo 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9. constant multiply (8 x 16 or 16 x 8). dual variable multiply (8 x 8). n embedded 32-bit internal system bus plus 4-bit par- ity interconnects fpga logic, microprocessor inter- face (mpi), embedded ram blocks, and embedded backplane transceiver blocks with 100 mhz bus per- formance. included are built-in system registers that act as the control and status center for the device. * pa l is a trademark of advanced micro devices, inc.
6 6 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc programmable features (continued) n built-in testability: full boundary scan ( ieee 1149.1 and draft 1149.2 jtag). programming and readback through boundary scan port compliant to ieee draft 1532:d1.7. ts_all testability function to 3-state all i/o pins. new temperature-sensing diode. system features n pci local bus compliant for fpga i/os. n improved powerpc * 860 and powerpc ii high-speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status; as well as for a general-purpose inter- face to the fpga logic, rams, and embedded back- plane transceiver blocks. glueless interface to synchronous powerpc processors with user-config- urable address space provided. n new embedded amba ? specification 2.0 ahb sys- tem bus ( arm ? processor) facilitates communication among the microprocessor interface, configuration logic, embedded block ram, fpga logic, and back- plane transceiver logic. n new network plls meet itu-t g.811 specifications and provide clock conditioning for ds-1/e-1 and sts-3/stm-1 applications. n flexible general purpose pplls offer clock multiply (up to 8x), divide (down to 1/8x), phase shift, delay compensation, and duty cycle adjustment combined. n variable size bused readback of configuration data capability with the built-in microprocessor interface and system bus. n internal, 3-state, and bidirectional buses with simple control provided by the slic. n new clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for or4e4). n new local clock routing structures allow creation of localized clock trees. n new edge clock routing supports at least six fast edge clocks per side of the device n new double-data rate (ddr) and zero-bus turn- around (zbt) memory interfaces support the latest high-speed memory interfaces. n new 2x/4x uplink and downlink i/o capabilities inter- face high-speed external i/os to reduced speed internal logic. n orca foundry 2000 development system software. supported by industry-standard cae tools for design entry, synthesis, simulation, and timing analysis. n meets universal test and operations phy interface for atm (utopia) levels 1, 2, and 3. also meets proposed specifications for utopia level 4 for 10 gbits/s interfaces. * powerpc is a registered trademark of international business machines, inc. ? amba is a trademark, and arm is a registered trademark of advanced risc machines limited.
lucent technologies inc. 7 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc descri p tion what is an fpsc? fpscs, or field-programmable system chips, are devices that combine field-programmable logic with asic or mask-programmed logic on a single device. fpscs provide the time to market and the flexibility of fpgas, the design effort savings of using soft intellec- tual property (ip) cores, and the speed, design density, and economy of asics. fpsc overview lucents series 4 fpscs are created from series 4 orca fpgas. to create a series 4 fpsc, several col- umns of programmable logic cells (see fpga logic overview section for fpga logic details) are added to an embedded logic core. other than replacing some fpga gates with asic gates, at greater than 10:1 effi- ciency, none of the fpga functionality is changedall of the series 4 fpga capability is retained: embedded block rams, mpi, pcms, boundary scan, etc. the col- umns of programmable logic are replaced at the right of the device, allowing pins from the replaced columns to be used as i/o pins for the embedded core. the remainder of the device pins retain their fpga func- tionality. the embedded cores can take many forms and gener- ally come from lucent technologies asic libraries. other offerings allow customers to supply their own core functions for the creation of custom fpscs. fpsc gate counting the total gate count for an fpsc is the sum of its embedded core (standard-cell/asic gates) and its fpga gates. because fpga gates are generally expressed as a usable range with a nominal value, the total fpsc gate count is sometimes expressed in the same manner. standard-cell asic gates are, however, 10 to 25 times more silicon-area efficient than fpga gates. therefore, an fpsc with an embedded function is gate equivalent to an fpga with a much larger gate count. fpga/embedded core interface the interface between the fpga logic and the embed- ded core has been enhanced to allow for a greater number of interface signals than on previous fpsc achitectures. compared to bringing embedded core signals off-chip, this on-chip interface is much faster and requires less power. all of the delays for the inter- face are precharacterized and accounted for in the orca foundry development system. series 4 based fpscs expand this interface by provid- ing a link between the embedded block and the multi- master 32-bit system bus in the fpga logic. this sys- tem bus allows the core easy access to many of the fpga logic functions including the embedded block rams and the microprocessor interface. clock spines also can pass across the fpga/embed- ded core boundary. this allows for fast, low-skew clock- ing between the fpga and the embedded core. many of the special signals from the fpga, such as done and global set/reset, are also available to the embed- ded core, making it possible to fully integrate the embedded core with the fpga as a system. for even greater system flexibility, fpga configuration rams are available for use by the embedded core. this allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality simply by recon- figuring the device. orca foundry 2000 development system the orca foundry 2000 development system is used to process a design from a netlist to a configured fpga. this system is used to map a design onto the orca architecture and then place and route it using orca foundrys timing-driven tools. the development system also includes interfaces to, and libraries for, other popular cae tools for design entry, synthesis, simulation, and timing analysis. the orca foundry 2000 development system inter- faces to front-end design entry tools and provides the tools to produce a configured fpga. in the design flow, the user defines the functionality of the fpga at two points in the design flow: design entry and the bit- stream generation stage. recent improvements in orca foundry allow the user to provide timing requirement information through logical preferences only, thus, the designer is not required to have physical knowledge of the implementation.
8 8 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc description (continued) following design entry, the development systems map, place, and route tools translate the netlist into a routed fpga. a floorplanner is available for layout feedback and control. a static timing analysis tool is provided to determine device speed and a back-annotated netlist can be created to allow simulation and timing. timing and simulation output files from orca foundry are also compatible with many third-party analysis tools. its bit stream generator is then used to generate the configuration data which is loaded into the fpgas internal configuration ram, embedded block ram, and/or fpsc memory. when using the bit stream generator, the user selects options that affect the functionality of the fpga. com- bined with the front-end tools, orca foundry pro- duces configuration data that implements the various logic and routing options discussed in this data sheet. fpsc design kit development is facilitated by an fpsc design kit which, together with orca foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an fpsc implementation. included in the kit are the fpsc configuration manager, synopsys smart model *, and complete online documentation. the kit's software cou- ples with orca foundry, providing a seamless fpsc design environment. more information can be obtained by visiting the orca website or contacting a local sales office, both listed on the last page of this docu- ment. fpga logic overview the orca series 4 architecture is a new generation of sram-based programmable devices from lucent technologies microelectronics group. it includes enhancements and innovations geared toward todays high-speed systems on a single chip. designed with networking applications in mind, the series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 4 devices contain many new patented enhancements and are offered in a variety of packages and speed grades. the hierarchical architecture of the logic, clocks, rout- ing, ram, and system level blocks create a seamless merge of fpga and asic designs. modular hardware and software technologies enable system-on-chip inte- gration with true plug and play design implementation. the architecture consists of four basic elements: pro- grammable logic cells (plcs), programmable i/o cells (pios), embedded block rams (ebrs), and system- level features. these elements are interconnected with a rich routing fabric of both global and local wires. an array of plcs are surrounded by common interface blocks which provide an abundant interface to the adja- cent plcs or system blocks. routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the pro- grammable logic core. each plc contains a pfu, slic, local routing resources, and configuration ram. most of the fpga logic is performed in the pfu, but decoders, pa l -like functions, and 3-state buffering can be performed in the slic. the pios provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplex- ing, uplink and downlink functions, and other functions on two output signals. large blocks of 512 x 18 quad- port ram compliment the existing distributed pfu memory. the ram blocks can be used to implement ram, rom, fifo, multiplier, and cam. some of the other system-level functions include the mpi, plls, and the embedded system bus (esb). plc logic each pfu within a plc contains eight 4-input (16-bit) luts, eight latches/ffs, and one additional flip-flop that may be used independently or with arithmetic func- tions. the pfu is organized in a twin-quad fashion; two sets of four luts and ffs that can be controlled indepen- dently. each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects. luts may also be combined for use in arithmetic func- tions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be configured as a synchronous 32 x 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset. * synopsys smart model is a registed trademark of synopsys, inc.
lucent technologies inc. 9 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc description (continued) the slic is connected from plc routing resources and from the outputs of the pfu. it contains eight 3- state, bidirectional buffers, and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert to perform pa l -like functions. the 3- state drivers in the slic and their direct connections from the pfu outputs make fast, true, 3-state buses possible within the fpga, reducing required routing and allowing for real-world system performance. programmable i/o the series 4 pio addresses the demand for the flexi- bility to select i/os that meet system interface require- ments. i/os can be programmed in the same manner as in previous orca devices, with the additional new features which allow the user the flexibility to select new i/o types that support high-speed interfaces. each pio contains four programmable i/o pads and is interfaced through a common interface block to the fpga array. the pio is split into two pairs of i/o pads with each pair having independent clock enables, local set/reset, and global set/reset. on the input side, each pio contains a programmable latch/flip-flop which enables very fast latching of data from any pad. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer with a pfu. on the output side of each pio, an output from the plc array can be routed to each output flip-flop, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of out- put signals and other functions of two output signals. the output ff, in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the out- put buffer signal can be inverted, and the 3-state con- trol can be made active-high, active-low, or always enabled. in addition, this 3-state signal can be regis- tered or nonregistered. the series 4 i/o logic has been enhanced to include modes for speed uplink and downlink capabilities. these modes are supported through shift register logic, which divides down incoming data rates or multi- plies up outgoing data rates. this new logic block also supports high-speed ddr mode requirements where data is clocked into and out of the i/o buffers on both edges of the clock. the new programmable i/o cell allows designers to select i/os which meet many new communication stan- dards permitting the device to hook up directly without any external interface translation. they support tradi- tional fpga standards as well as high-speed, single- ended, and differential-pair signaling (as shown in table 1). based on a programmable, bank-oriented i/o ring architecture, designs can be implemented using 3.3 v, 2.5 v, 1.8 v, and 1.5 v referenced output levels. routing the abundant routing resources of the series 4 archi- tecture are organized to route signals individually or as buses with related control signals. both local and global signals utilize high-speed buffered and nonbuffered routes. one plc segmented (x1), six plc segmented (x6), and bused half chip (xhl) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated i/o pads, plls, or the plc logic. secondary and edge-clock routing is available for fast regional clock or control signal routing for both internal regions and on device edges. secondary clock routing can be sourced from any i/o pin, plls, or the plc logic. the improved routing resources offer great flexibility in moving signals to and from the logic core. this flexibil- ity translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to specific pins.
10 10 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc system level features the series 4 also provides system-level functionality by means of its microprocessor interface, embedded sys- tem bus, quad-port embedded block rams, universal programmable phase-locked loops, and the addition of highly tuned networking specific phase-locked loops. these functional blocks allow for easy glueless system interfacing and the capability to adjust to varying condi- tions in todays high-speed networking systems. microprocessor interface the mpi provides a glueless interface between the fpga and powerpc microprocessors. programmable in 8-, 16-, and 32-bit interfaces with optional parity to the motorola * powerpc 860 bus, it can be used for con- figuration and readback, as well as for fpga control and monitoring of fpga status. all mpi transactions utilize the series 4 embedded system bus at 66 mhz performance. a system-level microprocessor interface to the fpga user-defined logic following configuration, through the system bus, including access to the embedded block ram and general user-logic, is provided by the mpi. the mpi supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data fifos. transfer accesses can be single beat (1 x 4-bytes or less), 4-beat (4 x 4- bytes), 8-beat (8 x 2-bytes), or 16-beat (16 x 1-bytes). system bus an on-chip, multi-master, 8-bit system bus with 1-bit parity facilitates communication among the mpi, config- uration logic, fpga control, and status registers, embedded block rams, as well as user logic. utilizing the amba specification rev 2.0 ahb protocol, the embedded system bus offers arbiter, decoder, master, and slave elements. master and slave elements are also available for the user-logic and embedded back- plane transceiver portion of the 8850. the system bus control registers can provide control to the fpga such as signalling for reprogramming, reset functions, and pll programming. status registers mon- itor init, done, and system bus errors. an interrupt controller is integrated to provide up to eight possible interrupt resources. bus clock generation can be sourced from the microprocessor interface clock, con- figuration clock (for slave configuration modes), internal oscillator, user clock from routing, or from the port clock (for jtag configuration modes). * motorola is a registered trademark of motorola, inc. phase-locked loops up to eight plls are provided on each series 4 device, with four plls generally provided for fpscs. program- mable plls can be used to manipulate the frequency, phase, and duty cycle of a clock signal. each ppll is capable of manipulating and conditioning clocks from 20 mhz to 420 mhz. frequencies can be adjusted from 1/8x to 8x, the input clock frequency. each programma- ble pll provides two outputs that have different multi- plication factors but can have the same phase relationships. duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. an automatic input buffer delay compensation mode is available for phase delay. each ppll provides two out- puts that can have programmable (12.5% steps) phase differences. additional highly-tuned and characterized, dedicated phase-locked loops (dplls) are included to ease sys- tem designs. these dplls meet itu-t g.811 primary- clocking specifications and enable system designers to very tightly target specified clock conditioning not tradi- tionally available in the universal pplls. initial dplls are targeted to low-speed networking ds1 and e1, and also high-speed sonet/sdh networking sts-3 and stm-1 systems. these dplls are typically not included on fpsc devices and are not found on the ort8850 family embedded block ram new 512 x 18 quad-port ram blocks are embedded in the fpga core to significantly increase the amount of memory and compliment the distributed pfu memo- ries. the ebrs include two write ports, two read ports, and two byte lane enables which provide four-port operation. optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus. additional logic has been incorporated to allow signifi- cant flexibility for fifo, constant multiply, and two-vari- able multiply functions. the user can configure fifo blocks with flexible depths of 512k, 256k, and 1k includ- ing asynchronous and synchronous modes and pro- grammable status and error flags. multiplier capabilities allow a multiple of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16-bit output). on-the-fly coefficient modifications are available through the second read/ write port. two 16 x 8-bit cams per embedded block can be implemented in single match, multiple match, and clear modes. the ebrs can also be preloaded at device configuration time.
lucent technologies inc. 11 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc system level features (continued) configuration the fpgas functionality is determined by internal con- figuration ram. the fpgas internal initialization/con- figuration circuitry loads the configuration data at power up or under system control. the configuration data can reside externally in an eeprom or any other storage media. serial eeproms provide a simple, low pin- count method for configuring fpgas. the ram is loaded by using one of several configura- tion modes. supporting the traditional master/slave serial, master/slave parallel, and asynchronous periph- eral modes, the series 4 also utilizes its microproces- sor interface and embedded system bus to perform both programming and readback. daisy chaining of multiple devices and partial reconfiguration are also permitted. other configuration options include the initialization of the embedded-block ram memories and fpsc mem- ory as well as system bus options and bit stream error checking. programming and readback through the jtag (ieee 1149.2 ) port is also available meeting in- system programming (isp) standards ( ieee 1532 draft). additional information contact your local lucent technologies representative for additional information regarding the orca series 4 fpga devices, or visit our website at: http://www.lucent.com/orca
12 12 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ort8850 overview device layout the ort8850 fpsc provides a high-speed backplane transceiver combined with fpga logic. the device is based on 1.5 v or4e2 or or4e6 fpgas. the or4e2 has a 26 x 24 array of programmable logic cells (plcs) and the or4e6 has a 46 x 44 array . for the ort8850, several columns of plcs in these arrays were replaced with the embedded backplane transceiver core. the ort8850 embedded core comprises a long haul interface macro and three rapidio macros for intra- board chip-to-chip or backplane communication. the long-haul interface includes the high-speed interface (hsi) macrocell, the synchronous transport module (stm) macrocell, and a 8b/10b encoder/decoder. the eight full-duplex channels perform data transfer, scram- bling/descrambling or encoding/decoding, and framing at the rate of 850 mbits/s. each rapidio block has a transmit and receive section which each contain 1 lvds clock buffer pair, 1 lvds start-of-cell buffer pair, and 8 lvds clock buffer pairs which are double edge clocked by the corresponding clock. figure 1 shows the ort8850 block diagram. backplane transceiver interface the advantage of the ort8850 fpsc is to bring spe- cific networking functions to an early market presence using programmable logic in a system. the 850 mbits/s backplane transceiver core allows the ort8850 to communicate across a backplane or on a given board at an aggregate speed of 6.8 gbits/s, pro- viding a physical medium for high-speed asynchronous serial data transfer between system devices. this device is intended for, but not limited to, connecting ter- minal equipment in sonet/sdh, atm, and ip sys- tems. the backplane transceiver core is used to support a 6.8 gbits/s interface for backplane connection to a mate tadm042g5 device or other sonet devices such as redundant central crossconnect. the interface is implemented as an eight channel 850 mbits/s lvds links. the hsi macrocell is used for clock/data recovery (cdr) and serialize/deserialize between the 106.25 mhz byte-wide internal data buses and the 850 mbits/s serial lvds links. for a 622 mbits/s sonet stream, the hsi will perform clock and data recovery (cdr) and mux/demux between 77.76 mhz byte-wide internal data buses and 622 mbits/s serial lv d s l i n k s . each 850 mbits/s serial link uses a pseudo-sonet protocol. sonet a1/a2 framing is used on the link to detect the 8 khz frame location. the link is also scram- bled using the standard sonet scrambler definition to ensure proper transitions on the link for improved cdr performance. selectable transport overhead (toh) bytes are insertable in the transmit direction. all the selectable bytes are inserted from software program- mable registers that are accessed via a microprocessor interface. elastic buffers (fifos) are used to align each incoming sts-12 link to the 77.76 mhz clock and 8 khz frame. these fifos will absorb delay variations between the four 622 mbits/s links due to timing skews between cards and along backplane traces. for greater varia- tions, a streamlined pointer processor (pointer mover) within the stm macro will align the 8 khz frames regardless of their incoming frame position. the backplane transceiver allows for sonet scram- bling and frame alignment or 8-bit/10-bit (8b/10b) encoding/decoding. sonet has the advantage of reduced overhead (3.3% overhead for sonet vs. 25% overhead for 8b/10b). 8b/10b has the advantage of faster synchronization (a few bytes of transferred data for 8b/10b vs. up to 500 m s for four frames of data for sonet). the effective data transfer rate for scrambled sonet is greater than 800 mbits/s while the effective data transfer rate for 8b/10b is greater than 680 mbits/s. frame synchronization and multi channel alignment is provided in 8b/10b mode through the use of special k characters. figure 2 shows the architecture of the ort8850 back- plane transceiver core.
lucent technologies inc. 13 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ort8850 overview (continued) 5-8113(f) figure 1. orca ort8850 block diagram standard fpga i/os orca series 4 fpga logic lvds i/os 311 mhz ddr interface 8-bit/10-bit encoder 8-bit/10-bit decoder pseudo- sonet framer pointer mover scrambling fifo alignment selected toh clock/data recovery byte- wide data lvds 850 mbits/s data 850 mbits/s data 8 full- serial duplex channels lvds i/os lvds i/os i/os ( rapidio ) 311 mhz ddr interface ( rapidio ) 311 mhz ddr interface ( rapidio )
14 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ort8850 overview (continued) figure 2. high level diagram of ort8850 transceiver io ring soft cntl txd_a[7:0] txsoc_a txclk_a rxd_a[7:0] rxsoc_a rxclk_a tr a n s m i t rstn_rx_a csysenb_a txd[31:0] txsoc ytristn_a utxtristn_a rstn_utx_a utxd_a[31:0] utxsoc_a pll wcd fpga wutxclk_fpga zrxd_a[31:0] zrxsoc_a zrxsocviol_a zrxalnviol_a zrxclk_a wrxclk_a_fpga pfclk stm macro + cdr 8 8 tx rx 8 8 2 1 4 12x8 8 10 9 1 9x8 (8 channels) 8 data + par 8b/10b k-control inputs line_fp, sys_fp sys_clk prot_sw 8 data + spe + c1j1 + par +en 8 recovered clks toh block 8 data + toh_ck_en + toh_fp 8 data + toh_ck_en toh_clk cdr + stm rapidio a up interface pwruprst from fpga (goes to all blocks) system bus fifo tr a n s m i t module receive module soft cntl txd_b[7:0] txsoc_b txclk_b rxd_b[7:0] rxsoc_b rxclk_b tr a n s m i t rstn_rx_b csysenb_b txd[31:0] txsoc ytristn_b utxtristn_b rstn_utx_b utxd_b[31:0] utxsoc_b wcd wutxclk_fpga zrxd_b[31:0] zrxsoc_b zrxsocviol_b zrxalnviol_b zrxclk_b wrxclk_b_fpga pfclk rapidio b fifo tr a n s m i t module receive module soft cntl txd_c[7:0] txsoc_c txclk_c rxd_c[7:0] rxsoc_c rxclk_c tr a n s m i t rstn_rx_c csysenb_c txd[31:0] txsoc ytristn_c utxtristn_c rstn_utx_c utxd_c[31:0] utxsoc_c wcd wutxclk_fpga zrxd_c[31:0] zrxsoc_c zrxsocviol_c zrxalnviol_c zrxclk_c wrxclk_c_fpga pfclk rapidio c fifo tr a n s m i t module receive module soft cntl 8 soft cntl 8
lucent technologies inc. 15 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ort8850 overview (continued) hsi interface the high-speed interconnect (hsi) macrocell is used for clock/data recovery and mux/demux between 106.25 mhz byte-wide internal data buses and 850 mbits/s external serial links. the hsi interface receives eight 850 mbits/s serial input data streams from the lvds inputs and provides eight independent 106.25 mhz byte-wide data streams and recovered clock to the stm macro. there is no requirement for bit alignment since sonet type fram- ing will take place inside the ort850 core. for trans- mit, the hsi converts four byte-wide 106.25 mhz data streams to serial streams at 850 mbits/s at the lvds outputs. stm macrocell the stm portion of the embedded core consists of transmitter (tx) and receiver (rx) sections. the receiver receives eight byte-wide data streams at 106.25 mhz and the associated clocks from the hsi. in the rx section, the incoming streams are sonet framed and descrambled before they are written into a fifo, which absorbs phase and delay variations and allows the shift to the system clock. the toh is then extracted and sent out on the eight serial ports. the pointer mover consists of three blocks: pointer inter- preter, elastic store, and pointer generator. the pointer interpreter finds the synchronous transport signal (sts) synchronous payload envelopes (spe) and places it into a small elastic store from which the pointer generator will produce eight byte-wide sts-12 streams of data that are aligned to the system timing pulse. in the tx section, transmitted data for each channel is received through a parallel bus and a serial port from the fpga circuit. toh bytes are received from the serial input port and can be optionally inserted from programmable registers or serial inputs to the sts-12 frame via the toh processor. each of the eight parallel input buses is synchronized to a free-running system clock. then the spe and toh data is transferred to the hsi. the stm macrocell also has a scrambler/descrambler disable feature, allowing the user to disable the scram- bler of the transmitter and the descrambler of the receiver. also, unused channels can be disabled to reduce power dissipation. 8b/10b encoder/decoder the ort8850 facilitates high-speed serial transfer of data in a variety of applications including gigabit ether- net, fibre channel, serial backplanes, and proprietary links. the device provides 8b/10b coding/decoding for each channel. the 8b/10b transmission code includes serial encoding/decoding rules, special characters and error detection. information to be transmitted over a fibre shall be encoded eight bits at a time into a 10-bit transmission character and then sent serially. the 10-bit transmis- sion characters support all 256 eight-bit combinations. some of the remaining transmission characters referred to as special characters, are used for functions which are to be distinguishable from the contents of a frame. fpga interface the fpga logic will receive/transmit frame-aligned (optional for 8b/10b mode) streams of 106.25 mhz data (maximum of eight streams in each direction) from/to the backplane transceiver embedded core. all frames transmitted to the fpga will be aligned to the fpga frame pulse which will be provided by the fpga users logic to the stm macro. if the receive pointer mover and alignment fifos are bypassed, then each channel will provide its own receive clock and receive frame pulse signals. otherwise, all frames received from the fpga logic will be aligned to the system frame pulse that will be supplied to the stm macro from the fpga users logic. byte-wide parallel interface three byte-wide parallel interface are provided on the ort8850. each interface provides for transmit and receive of byte-wide data, one control signal and one clock. receive data is sampled on both edges of the receive clock and is converted to a 32-bit data bus which is single-edge clocked by a half-speed clock for transfer to the fpga logic. maximum transmit/receive clock rate is 311 mhz and 155 mhz for the internal fpga clock. this allows for a 622 mbits/s link data transfer rate. other functions provied include a check for a minimum number of transferred bytes. the first byte-wide interface ( rapidio a in figure 2) is always available. the other two interfaces ( rapidio b and rapidio c) are available when the 850 mbits/s serial links are not being used.
16 16 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ort8850 overview (continued) fpsc configuration configuration of the ort8850 occurs in two stages, fpga bit stream configuration, and embedded core setup. fpga configuration prior to becoming operational, the fpga goes through a sequence of states, including powerup, initialization, configuration, start-up, and operation. the fpga logic is configured by standard fpga bitstream configura- tion means as discussed in the series 4 fpga data sheet. the options for the embedded core are set via registers that are accessed through the fpga system bus. optionally, the system bus can be driven by an external microprocessor via the mpi block. a simple microprocessor emulation soft intellectual property (ip) core that drives the system bus and uses very little of the fpga logic is available from lucent. this micropro- cessor core sets up the embedded core via a state machine and allows the ort8850 to work in an inde- pendent system without an external microprocessor interface. embedded core setup all options for the operation of the core are configured according to the device register map, which is included with the ort8850 fpsc simulation kit. during the powerup sequence, the ort8850 device (fpga programmable circuit and the core) is held in reset. all the lvds output buffers and other output buff- ers are held in 3-state. all flip-flops in core area are in reset state, with the exception of the boundry scan shift registers, which can only be reset by boundary scan reset. after powerup reset, the fpga can start configu- ration. during fpga configuration, the ort8850 core will be held in reset and all the local bus interface sig- nals forced high, but the following active-high signals (prot_switch_a, prot_switch_c, tx_toh_ck_en, sys_fp, line_fp) will be forced low. the core_ready signal sent from the embed- ded core to fpga is held low, indicating that the core is not ready to interact with fpga logic. at the end of the fpga configuration sequence, the core_ready sig- nal will be held low for six sys_clk cycles after done, tri_io and rst_n (core global reset) are high. then it will go active-high, indicating the embed- ded core is ready to function and interact with fpga programmable circuit. during fpga reconfiguration when done and tri_io are low, the core_ready signal sent from the core to fpga will be held low again to indicate the embedded core is not ready to interact with fpga logic. during fpga partial configu- ration, core_ready stays active. the same fpga configuration sequence described previously will repeat again. the initialization of the embedded core consists of two steps: register configuration and synchronization of the alignment fifo. in order to configure the embedded core, the registers need to be unlocked by writing 0xa0 to address 0x04 and writing 0x01 to address 0x05. control registers 0x04 and 0x05 are lock registers. if the output bus of the data, serial toh port, and toh clock and toh frame pulse are controlled by 3-state registers (the use of the registers for 3-state output control is optional; these output 3-state enable signals are brought across the local bus interface and available to the fpga side), the next step is to activate the 3- state output bus and signals by taking them to func- tional state from high-impedance state. this can be done by writing 0x01 to correspond bits of the channel registers 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0, and 0xc8. in addition, the synchronization of selected streams is recommended for some networking systems applica- tions. this is a resync of the alignment fifo after the enabled channels have a valid frame pulse. here are the following procedures: put all of the streams to be aligned, including disabled streams, into their required alignment mode. force ais-l in all streams to be syn- chronized (refer to register map, write 0x01 to db1 of register 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 and 0xc8). wait four frames. write a 0x01 to the fifo alignment resync register, bit db1 of register 0x06. wait four frames. release the ais-l in all streams (write 1 to db1 of register 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0, and 0xc8). this procedures allows normal data flow through the embedded core. synchronization of the alignment fifos in 8b/10b mode is similar and will be described in the next ver- sion of this datasheet.
lucent technologies inc. 17 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc generic backplane transceiver application synchronous transfer mode (stm) the combination of ort8850 and soft ip cores pro- vides a generic data moving solution for non-sonet applications. there is no requirement for sonet knowledge to the users. all that is needed is to supply the pseudo-sonet framer with data, clock, and a 8 khz frame pulse. the provision registers may also need to be set up, and this can be done through either the fpga mpi, or in a state machine in the fpga sec- tion (vhdl code available from lucent). the 8 khz frame pulse must be supplied to the sys_fp signal. for generic applications, the frame pulse can be created in fpga logic from the 77.76 mhz sys_clk using a simple resettable counter (the frame pulse should only be high for one cycle of the sys_clk). a vhdl core that automati- cally provides the 8 khz frame pulse is available from lucent. byte-wide data is then sent to each of the transmit channels as follows: the first 36 bytes trans- ferred will be invalid data (replaced by overhead), where the first byte is sent on the rising edge of sys_clk when sys_fp is high. the next 1044 byte positions can be filled with valid data. this will repeat a total of nine times (36 invalid bytes followed by 1044 valid bytes) at which time the next 8 khz frame pulse will be found. thus, 87 out of 90 (96.7%) of the data bytes sent are valid user data. the ort8850 also supports a transparent mode where only the first 24 bytes are invalid data (a1/a2 frame bytes) followed by 9,684 bytes of valid user data. on the receive side, an 8 khz pulse must again be sup- plied to sys_fp. in this case, however, only the signal dout_spe (where the 8 channels are labeled aa, ab, ac, ad, ba, bb, bc, and bd) must be monitored for each channel, where a high value on this signal means valid data. again 87 out 90 bytes received (96.7%) will be valid data. transparent mode is also supported for receive data. in order to provide an easy user interface to transfer arbitrary data streams through the ort8850, lucent provides a soft intellectual property (ip) core called the protocol independent framer, or pi-framer. this block transfers user format to the one described above and allows for smoothing/rate transfer of this user data. this framer works with a single channel at 850 mbits/s, two channels at 1.7 gbits/s, four channels at 3.4 gbits/s, or across eight channels at 6.8 gbit/s. 8b/10b mode the ort8850 facilitates high-speed serial transfer of data in a variety of applications including gigabit ether- net, fibre channel, serial backplanes, and proprietary links. in place of the stm interface, the 8850 also pro- vides 8b/10b coding/decoding for each channel. the 8b/10b transmission code includes serial encoding/ decoding rules, special characters, and error detection. transmitter description the data input to the transmitter of each channel is an eight-bit word and a k-control input. the k input is used to identify data or a special character. for each channel, the input data byte is clocked into a fifo. when k-control is 1, the data on the parallel input is mapped into its corresponding control character. the transmit fifos must be initialized upon the deassertion of the rst_n signal. receiver description clock recovery is performed by the hsi on the input data stream for each channel of the ort8850. the recovered data is then aligned to the 10-bit word boundary. word alignment is accomplished by detect- ing and aligning to the 8b/10b k28.5 codeword. the hsi will detect and align to either polariy of the k28.5. the 10-bit word aligned data is then passed to the alignment fifos. each receive channel provides a fifo in order to adjust for the skew between the chan- nels and ensure that the first valid data following the comma character (k28.5) is transmitted simultaneously from all the channels. channel sync block in order to account for skews between the channels, it is necessary to align multiple channels on the k28.5 (comma) character boundary. the sync algorithm assumes that either all 8 channels, two groups of four channels, or four groups of two channels will be aligned. the ort8850 powers up in the reset state in which no channel alignment is done. setup and use of the 8b/10b channel sync block is similar to that of the stm block.
18 18 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description hsi macro the 850 high speed interface (hsi) provides a physical medium for high speed asynchronous serial data trans- fer between asic devices. the devices can be mounted on the same pc board or mounted on differ- ent boards and connected through the shelf back- plane. the 850 cdr macro is an eight-channel clock- phase select (cps) and data retime function with serial-to-parallel demultiplexing for the incoming data stream and parallel-to-serial multiplexing for outgoing data. the macrocell can be used as a 8-channel or 16 channel configuration. the ort8850 uses an eight- channel hsi macro cell. the hsi macro consists of three functionally independent blocks: receiver, trans- mitter, and pll synthesizer as shown in figure 3. the pll synthesizer block generates the necessary or 850 mhz clock for operation from a 212 mhz, 106 mhz or 85 mhz reference. the pll synthesizer block is a common asset shared by all eight receive and transmit channels. the pll reference clock must match the interface frequency. the hsi_rx block receives a differential 850 mbits/s (or subrates 424 mbits/s, 212 mbits/s) serial data with- out clock at its lvds receiver input. based on data transitions, the receiver selects an appropriate 850 mhz clock phase for each channel to retime the data. the retimed data and clock are then passed to the demux (deserializer) module. demux module per- forms serial-to-parallel conversion and provides three possible parallel rates, 212 mbits/s, 106 mbits/s, or 85 mbits/s, where the 106 mbits/s data is used in sonet mode and the 85 mbits/s data is used in 8b/ 10b mode (212 mbits/s is currently unused). the hsi_tx block receives 212 mbits/s (unused), 106 mbits/s (sonet mode), or 85 mbits/s (8b/10b mode) parallel data at its input. mux (serializer) mod- ule performs a parallel-to-serial conversion using an 850 mhz clock provided by the pll/synthesizer block. the resulting 850 mbits/s serial data stream is then transmitted through the lvds driver. the loopback feature built into the hsi macro provides looping of the transmitter data output into the receiver input when desired. all rate examples described here are the maximum rates possible. the actual hsi internal clock rate is determined by the provided reference clock rate. for example, if a 78 mhz reference clock is provided, the hsi macro will operate at 622 mbits/s.
lucent technologies inc. 19 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) 5-8592 (f) figure 3. hsi functional block diagram tstmode tstshftld built-in rx cdr serial to parrallel demux select 848 mhz test clock/data alignment synthesizer pll loopbkch[(n C 1):0] ld[(n C 1):0]rx[9:0] mreset (master reset) ecsel exdnup etoggle tstphase tstclk bypass loopbken hdin[(n C 1):0] 848 mbits/s rext (tbd) pllpwrdn refck 212 mhz hdout[(n C1):0] (test) tstmux[9:0] lckrx[(n C 1):0] tstclk bypass (test) rxpwrdn[(n C 1):0] lckpll 212 mbits/s ld[(n C 1):0] tx[9:0] 1 2 n tx 1 2 n retime or 106 mhz or 85 mhz or 424 mbits/s or 212 mbits/s data or 106 mbits/s or 85 mbits/s parrallel to serial mux word align ten bit rc[1:0]ck[(n-1):0] encomma[(n-1):0] commadet[(n-1):0] mode halfrate[(n C 1):0] control quartrate[(n C 1):0] en10bit x4intfce (850 mhz) resettx resetrx 848 mbits/s or 424 mbits/s or 212 mbits/s data 212 mhz or 106 mhz or 85 mhz 212 mhz or 106 mhz or 85 mhz 212 mbits/s or 106 mbits/s or 85 mbits/s
20 20 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) stm transmitter (fpga -> backplane) the synchronous transport module (stm) portion of the embedded core consists of two slices: stm a and b. each stm slice has four sts-12 transmit channels which can be treated as a single sts-48 channel. in general, the transmitter circuit receives four byte-wide 77.76 mhz data from the fpga, which nominally rep- resents four sts-12 streams (a, b, c, and d). this data is synchronized to the system (reference) clock, and an 8 khz system frame pulse from the fpga logic. transport overhead bytes are then optionally inserted into these streams, and the streams are forwarded to the hsi. all byte timing pulses required to isolate indi- vidual overhead bytes (e.g., a1, a2, b1, d1d3, etc.) are generated internally based on the system frame pulse (sys_fp) received from the fpga logic. all streams operate byte-wide at 77.76 mhz in all modes. the toh processor operates from 25 mhz to 77.76 mhz and supports the following toh signals: a1 and a2 insertion and optional corruption; h1, h2, and h3 pass transparently; bip-8 parity calculation (after scrambling) and b1 byte insertion and optional corrup- tion (before scrambling); optional k1 and k2 insert; optional s1/m0 insert; optional e1/f1/e2 insert; optional section data communication channel (dcc, d1d3) and line data communication channel (dcc, d4d12) insertion (for intercard communications channel); scrambling of outgoing data stream with optional scrambler disabling; and optional stream dis- abling. all streams operate byte wide at 77.76 mhz (622 mbits/s) or 106.25 mhz (850 mbits/s) in all modes. when the ort8850 is used in non-networking applica- tions as a generic high-speed backplane data mover, the toh serial ports are unused or can be used for slow-speed off-channel communication between devices. an optional transparent mode is available where only the twelve a1 and twelve a2 bytes are used for frame alignment and synchronization. data received on the parallel bus is optionally scram- bled and transferred to lvds outputs. byte ordering information the stm macro slice (i.e., a, b) supports quad sts- 12, quad sts-3, and quad sts-1 modes of operation on the input/output ports. sts-48 is also supported but it must be received in the quad sts-12 format. when operating in quad sts-12 mode, each of the indepen- dent byte streams carries an entire sts-12 within it. figure 4 reveals the byte ordering of the individual sts-12 streams and for sts-48 operation. note that the recovered data will always continue to be in the same order as transmitted. 5-8574 (f) figure 4. byte ordering of input/output interface in sts-12 mode 12 24 36 48 9 21 33 45 6 18 30 42 3 15 27 39 11 23 35 47 8 20 32 44 5 17 29 41 2 14 26 38 10 22 34 46 7 19 31 43 4 16 28 40 1 13 25 37 1, 12 2, 12 3, 12 4, 12 1, 9 2, 9 3, 9 4, 9 1, 6 2, 6 3, 6 4, 6 1, 3 2, 3 3, 3 4, 3 1, 11 2, 11 3, 11 4, 11 1, 8 2, 8 3, 8 4, 8 1, 5 2, 5 3, 5 4, 5 1, 2 2, 2 3, 2 4, 2 1, 10 2, 10 3, 10 4, 10 1, 7 2, 7 3, 7 4, 7 1, 4 2, 4 3, 4 4, 4 1, 1 2, 1 3, 1 4, 1 sts-12 a sts-12 b sts-12 c sts-12 d sts-12 a sts-12 b sts-12 c sts-12 d sts-48 in quad sts-12 format quad sts-12
lucent technologies inc. 21 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) transport overhead for in band communication the toh byte can be used for in band configuration, service, and management since it is carried along the same channel as data. in ort8850, in band signaling can be efficiently utilized, since the total cost of over- head is only 3.3%. transport overhead insertion (serial link) the toh serial links are used to insert toh bytes into the transmit data. the transmit toh data and toh_clk_en get retimed by toh_clk in order to meet setup and hold specifications of the device. the retimed toh data is shifted into a 288-bit (36-byte by 8-bit) shift register and then multiplexed as an 8-bit bus to be inserted into the byte-wide data stream. insertion from these serial links or pass-through of toh from the byte-wide data is under software control. transport overhead byte ordering (fpga to backplane) in the transparent mode, spe and toh data received on parallel input bus is transferred, unaltered, to the serial lvds output. however, b1 byte of sts#1 is always replaced with a new calculated value (the 11 bytes following b1 are replaced with all zeros). also, a1 and a2 bytes of all sts-1s are always regenerated. toh serial port in not used in the transparent mode of operation. in the toh insert mode, spe bytes are transferred, unaltered, from the input parallel bus to the serial lvds output. on the other hand, toh bytes are received from the serial input port and are inserted in the sts- 12 frame before being sent to the lvds output. although all toh bytes from the 12 sts-1s are trans- ferred into the device from each serial port, not all of them get inserted in the frame. there are three hard- coded exceptions to the toh byte insertion: n framing bytes (a1/a2 of all sts-1s) are not inserted from the serial input bus. instead, they can always be regenerated. n parity byte (b1 of sts#1) is not inserted from the serial input bus. instead, it is always recalculated (the 11 bytes following b1 are replaced with all zeros). n pointer bytes (h1/h2/h3 of all sts-1s) are not inserted from the serial input bus. instead, they always flow transparently from parallel input to lvds output. in addition to the above hard-coded exceptions, the source of some toh bytes can be further controlled by software. when configured to be in pass-through mode, the specific bytes must flow transparently from the parallel input. note that blocks of 12 sts-1 bytes forming an sts-12 are controlled as a whole. there are 15 software controls per channel, as listed below: n source of k1 and k2 bytes of the 12 sts-1s (24 bytes) is specified by a control bit (per channel control). n source of s1 and m0 bytes of the 12 sts-1s (24 bytes) is specified by a control bit (per channel control). n source of e1, f1, e2 bytes of the sts-1s (36 bytes) is specified by a control it (per channel control). n source of d1 bytes of the sts-1s (12 bytes) is spec- ified by a control bit (per channel control). n source of d2 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). n source of d3 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). n source of d4 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). n source of d5 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). n source of d6 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). n source of d7 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). n source of d8 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). n source of d9 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). n source of d10 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). n source of d11 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). n source of d12 bytes of the 12 sts-1s (12 bytes) is specified by a control bit (per channel control). toh reconstruction is dependent on the transmitter mode of operation. in the transparent mode, toh bytes on lvds output are as shown in table 2. a new capability in the ort8850 allows the user to choose not to insert the b1 byte and the following eleven bytes of zeros. this option is also available for the a1 and a2 bytes.
22 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) table 2. transmitter toh on lvds output (transparent mode) in the toh insert mode of operation, toh bytes on lvds output are shown in table 3. this also shows the order in which data is transferred to the serial toh interface, starting with the must significant bit of the first a1 byte. the first bit of the first byte is replaced by an even parity check bit over all toh bytes from the previous toh frame. table 3. transmitter toh on lvds output (toh insert mode) a1/a2 frame insert and testing the a1 and a2 bytes provide a special framing pattern that indicates where a sts-1 begins in a bit stream. all 12 a1 bytes of each sts-12 are set to 0xf6, and all 12 a2 bytes of the sts-12 are set to 0x28 when not overrid- den with an user-specified value for testing. a1/a2 testing (corruption) is controlled per stream by the a1/a2 error insert register. when a1/a2 corruption detec- tion is set for a particular stream, the a1/a2 values in the corrupted a1/a2 value registers are sent for the number of frames defined in the corrupted a1/a2 frame count register. when the corrupted a1/a2 frame count register is set to zero, a1/a2 corruption will continue until the a1/a2 error insert register is cleared. this also allows alternate values to be set for a1 and a2 during normal operation. for the ort8850, it is optionally possible to not insert a1 and a2. on a per-device basis, the a1 and a2 byte values are set, as well as the number of frames of corruption. then, to insert the specified a1/a2 values, each channel has an enable register. when the enable register is set, the a1/a2 values are corrupted for the number specified in the number of frames to corrupt. to insert errors again, the per- channel fault insert register must be cleared, and set again. only the last a1 and the first a2 are corrupted. a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 b1 0 0 0 0 0 0 0 0 0 0 0 regenerated bytes. transparent bytes from parallel input port. a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 b1 0 0 0 0 0 0 0 0 0 0 0 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 e1 f1 f1 f1 f1 f1 f1 f1 f1 f1 f1 f1 f1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d1 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d2 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 d3 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k1 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 k2 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d4 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d5 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d6 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d7 d8 d8 d8 d8 d8 d8 d8 d8 d8 d8 d8 d8 d9 d9 d9 d9 d9 d9 d9 d9 d9 d9 d9 d9 d10 d10 d10 d10 d10 d10 d10 d10 d10 d10 d10 d10 d11 d11 d11 d11 d11 d11 d11 d11 d11 d11 d11 d11 d12 d12 d12 d12 d12 d12 d12 d12 d12 d12 d12 d12 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 s1 m0 m0 m0 m0 m0 m0 m0 m0 m0 m0 m0 m0 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 e2 regenerated bytes. inserted or transparent bytes. blocks of 12 sts-1 bytes are controlled as a whole. there are 15 controls/channel: k1/k2, s1/m0, e1/f1/e2, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12. transparent bytes (from parallel input port). inserted bytes from toh serial input port.
lucent technologies inc. 23 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) b1 calculation and insertion a bit interleaved parity C8 (bip-8) error check set for even parity over all the bits of an sts-1 frame. b1 is defined for the first sts-1 in an sts-n only, the b1 cal- culation block computes a bip-8 code, using even par- ity over all bits of the previous sts-12 frame after scrambling and is inserted in the b1 byte of the current sts-12 frame before scrambling. per-bit b1 corruption is controlled by the force bip-8 corruption register (reg- ister address 0f). for any bit set in this register, the corresponding bit in the calculated bip-8 is inverted before insertion into the b1 byte position. each stream has an independent fault insert register that enables the inversion of the b1 bytes. b1 bytes in all other sts- 1s in the stream are filled with zeros. for the ort8850, it is optionally possible to not insert b1 and the subse- quent eleven bytes of zeros. stream disable when disabled via the appropriate bit in the stream enable register, the prescrambled data for a stream is set to all ones, feeding the hsi. the hsi macro is pow- ered down on a per-stream basis, as are its lvds out- puts. scrambler the data stream is scrambled using a frame-synchro- nous scrambler with a sequence length of 127. the scrambling function can be disabled by software. the generating polynomial for the scrambler is 1 + x 6 + x 7 . this polynomial conforms to the standard sonet sts-12 data format. the scrambler is reset to 1111111 on the first byte of the spe (byte following the z0 byte in the twelfth sts-1). that byte and all subsequent bytes to be scrambled are exclusive-ored, with the output from the byte-wise scrambler. the scrambler runs continuously from that byte on throughout the remainder of the frame. a1, a2, j0, and z0 bytes are not scrambled. system frame pulse and line frame pulse system frame pulse (for transmitter) and line frame pulse (for receiver) are generated in fpga logic. a1/a2 framing is used on the link for locating the 8 khz frame location. all frames sent to the fpga are aligned to the fpga frame pulse line_fp which is provided by the fpga to the stm macro. all frames sent from the fpga to the stm will be aligned to the frame pulse sys_fp that is supplied to the stm macro. in either direction, the system frame pulse and line frame pulse are active for one system clock cycle, indicating the location of a1 byte of sts#1. they are common to all eight channels except when the pointer mover and alignment fifos are bypassed. in that case, a line frame pulse for each receive channel is generated by the stm macro and passed to the fpga interface. repeater this block is essentially the inverse of the sampler block . it receives byte wide sts-12 rate data from the toh insert block. in order to support the quad sts-1 and sts-3 modes of operation the hsi (622 mbits/s) can be connected to a slower speed device (e.g., 155 mbits/s or 52 mbits/s). the purpose of this block is to rearrange the data being fed to the hsi so that each bit is transmitted four or twelve times thus simulating 155 mbits/s or 51.84 mbits/s serial data. for example, in sts-3 mode the incoming sts-12 stream is com- posed of four identical sts-3s so only every fourth byte is used. the bit expansion process takes a single byte and stretches it to take up four bytes each consisting of 4 copies of the 8 bits from the original byte. in sts-1 mode, every twelfth byte is used and 4 groups of 3 bytes of the form aaaaaaaa, aaaabbbb & bbbbbbbb are forwarded to the hsi. an alternate method for supplying sts-1 mode is to set the hsi to run at 207.36 mhz and using the four times repeater function.
24 24 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) stm receiver (backplane -> fpga) each of the two stm slices of the ort8850 has four receiving channels that can be treated as one sts-48 stream, or treated as independent channels. incoming data is received through lvds serial ports at the data rate of 622 mbits/s. the receiver can handle the data streams with frame offsets of up to 12 bytes which would be due to timing skews between cards and along backplane traces. the received data streams are pro- cessed in the hsi and the stm, and then passed through the cic boundary to the fpga logic. framer block the framer block takes byte-wide data from the hsi, and outputs a byte-aligned, byte-wide data stream and 8 khz sync pulse. the framer algorithm determines the out-of-frame/in-frame status of the incoming data and will cause interrupts on both an errored frame and an out-of-frame (oof) state. the framer detects the a1/ a2 framing pattern and generates the 8 khz frame pulse. when the framer detects oof, it will generate an interrupt. also, the framer detects an errored frame and increments an a1/a2 frame error counter. the counter can be monitored by a processor to compile perfor- mance status on the quality of the backplane. because the ort8850 is intended for use between it and another ort8850 or other devices via a back- plane, there is only one errored frame state. thus after two transitions are missed, the state machine goes into the oof state and there is no severely errored frame (sef) or loss-of-frame (lof) indication. b1 calculate and descramble (backplane -> fpga) each rx block receives byte-wide scrambled 77.76 mhz data and a frame sync from the framer. since each hsi is independently clocked, the rx block operates on individual streams. timing signals required to locate overhead bytes to be extracted are generated internally based on the frame sync. the rx block pro- duces byte-wide (optionally) descrambled data and an output frame sync for the alignment fifo block. the frame sync signals are also sent to the fpga logic for use when the alignment fifo block is bypassed. the b1 calculation block computes a bip-8 (bit inter- leaved parity 8 bits) code, using even parity over all bits of the previous sts-12 frame before descrambling; this value is checked against the b1 byte of the current frame after descrambling. a per-stream b1 error counter is incremented for each bit that is in error. the error counter may be read via the cpu interface. descrambling. the streams are descrambled using a frame synchronous descrambler with a sequence length of 127 with a generating polynomial of 1 + x 6 + x 7 . the a1/a2 framing bytes, the section trace byte (j0) and the growth bytes (z0) are not descrambled. the descrambling function can be disabled by software. sampler. this block operates on the byte-wide data directly from the hsi macro. the hsi external interface always runs at 622 mbits/s (sts-12), or 850 mbits/s, but it can be connected directly to a 155 mbits/s sts-3 stream or a 51.84 mbits/s sts-1 stream. if connected to either a 155 mbits/s or 51.84 mbits/s stream, each incoming data is received either 4 or 12 times respec- tively. this block is used to return the byte stream to the expected sts-12 format. the mode of operation is controlled by a register and can either be sts-12 (pass-through), sts-3 (every 4th bit), or sts-1 (every 12th bit). the output from this block is not bit aligned (i.e., and 8 bit sample does not necessarily contain an entire sonet byte) but it is in standard sonet sts- 12 format (i.e., four sts-3s or 12 sts-1s), and is suit- able for framing. ais-l insertion. alarm indication signal (ais) is a con- tinuous stream of unframed 1s sent to alert down- stream equipment that the near-end terminal has failed, lost its signal source, or has been temporarily taken out of service. if enabled in the ais_l force regis- ter, ais-l is inserted into the received frame by writing all ones for all bytes of the descrambled stream. ais-l insertion on out-of-frame. if enabled via a register, ais-l is inserted into the received frame by writing all ones for all bytes of the descrambled stream when the framer indicates that an out-of-frame condi- tion exists. internal parity generation even parity is generated on all data bytes and is routed in parallel with the data to be checked before the pro- tection switch mux at the parallel output. fifo alignment (backplane -> fpga) the alignment fifo allows the transfer of all data to the system clock. the fifo sync block (figure 5) allows the system to be configured to allow the frame alignment of multiple slightly varying data streams. this optional alignment ensures that matching sts-12 streams will arrive at the fpga end in perfect data sync. the frame alignment is configurable to allow for the possibility of fully independent (i.e., total frame mis- alignment) sts-12s.
lucent technologies inc. 25 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) 5-8577 (f) figure 5. interconnect of streams for fifo alignment the incoming data from the hsi (also referred to as cdrm850) can be separated into 4 sts-12 channels (a, b, c, and d) per slice. thus there are sts-12 chan- nels aa to ad from slice a of the stm and sts-12 channels ba to bd of slice b. these streams can be frame-aligned in the following patterns: in sts-48 mode, all four sts-12s of each stm slice are aligned with each other (i.e., aa, ab, ac, ad). optionally, in sts-48 mode, all eight sts-12s (stms a and b) can be aligned (to allow hitless switching at the sts-48 level). multiple devices can be aligned to enable sts- 192 or higher modes. streams can also be aligned on a twin sts-12 basis. there is also a provision to allow certain streams to be disabled (i.e., not producing inter- rupts or affecting synchronization). these streams can be enabled at a later time without disrupting other streams. if the selected stream needs to be a part of a bigger group (i.e., stm a), then either the entire group must be resynched or the affected stream must have been in the correct mode (i.e., align all stm a) when the initial synchronization was performed. as long as all four streams in stm a are in the correct mode when synchronization takes place then those streams may be enabled or disabled without affecting synchroniza- tion. these streams can be frame aligned in the patterns shown in figure 6, figure 7, and figure 8. 0673(f) figure 6. example of intra-stm alignment 0674 figure 7. example of inter-stm alignment 0675 figure 8. example of twin sts-12 stream alignment sts-12 stream aa sts-12 stream ab sts-12 stream ac sts-12 stream ad sts-12 stream ba sts-12 stream bb sts-12 stream bc fifo sync sts-12 stream bd stm slice a stm slice b stm a stream a stm a stream b stm a stream c stm a stream d stm b stream a stm b stream b stm b stream c stm b stream d all 4 alignment of stm a and stm b stm a stream a stm a stream b stm a stream c stm a stream d stm b stream a stm b stream b stm b stream c stm b stream d t 0 t 1 stm a stream a stm a stream b stm a stream c stm a stream d stm b stream a stm b stream b stm b stream c stm b stream d all 8 alignment of stm a and stm b stm a stream a stm a stream b stm a stream c stm a stream d stm b stream a stm b stream b stm b stream c stm b stream d t 0 stm a stream a stm a stream b stm a stream c stm a stream d stm b stream a stm b stream b stm b stream c stm b stream d twins alignment of streams a and c t 0 stm a stream a stm a stream b stm a stream c stm a stream d stm b stream a stm b stream b stm b stream c stm b stream d t 1
26 26 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) the fifo block consists of a 24-bit by 10-bit fifo per link. this fifo is used to align up to 154.3 ns of inter- link skew and to transfer to the system clock. the fifo sync circuit takes metastable hardened frame pulses from the write control blocks and produces sync signals that indicate when the read control blocks should begin reading from the first fifo location. on top of the sync signals, this block produces an error indicator which indicates that the signals to be aligned are too far apart for alignment (i.e., greater than 18 clocks apart). sync and error signals are sent to read control block for alignment. the read control block is synched only once on start-up; any further synchronization is software controlled. the action of resynching a read control block will always cause loss of data. a register allows the read control block to be resynched. link alignment the general operation of the link alignment algorithm is to wait 12 clocks (i.e., half the fifo) from the arriving frame pulse and then signal the read control block to begin reading. for perfectly aligned frame pulses across the links, it is simply a matter of counting down 12 and then signaling the read control block. the algorithm down counts by one until all of the frame pulses have arrived and then by two when they are all present. for example (figure 9), if all pulses arrive together, then alignment algorithm would count 24 (12 clocks); if, however, the arriving pulses are spread out over four clocks, then it would count one for the first four pulses and then two per clock afterward, which gives a total of 14 clocks between first frame pulse and the first read. this puts the center of arriving frame pulses at the halfway point in the buffer. this is the extent of the algorithm, and it has no facility for actively correcting problems once they occur. the write control block receives byte-wide data at 77.76 mhz and a frame pulse two clocks before the first a1 byte of the sts-12 frame. it generates the write address for the fifo block. the first a1 in every sts- 12 stream is written in the same location (address 0) in the fifo. also, a frame bit is passed through the fifo along with the first byte before the first a1 of the sts- 12. the read control block synchronizes the reading of the fifo for streams that are to be aligned. reading begins when the fifo sync signals that all of the appli- cable a1s and the appropriate margin have been writ- ten to the fifo. all of the read blocks to be synchronized begin reading at the same time and same location in memory (address 0). the alignment algorithm takes the difference between read address and write address to indicate the relative clock alignments between sts-12 streams. if this depth indication exceeds certain limits (12 clocks), then an interrupt is given to the microprocessor (alignment overflow). each sts-12 stream can be realigned by software if it gets too far out of line (this would cause a loss of data). for background applications that have less than 154.3 ns of interlink skew, misalignment will not occur. 5-8584 (f) figure 9. examples of link alignment 24-byte fifo 24-byte fifo all fps 12 clocks sync. pulse arrive together (writing begins) (reading begins) sync pulse (reading begins) last fp arrives 4 clocks first fp arrives (writing begins) 10 clocks perfectly aligned frames 4-byte spread in arriving frames
lucent technologies inc. 27 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) pointer mover block (backplane -> fpga) the pointer mover maps incoming frames to the line framing that is supplied by the fpga logic. there is a sepa- rate pointer mover for the two stm macro slices, a and b, each of which handles up to one sts-48 (4 channels). the k1/k2 bytes and h1-ss bits are also passed through to the pointer generator so that the fpga can receive them. the pointer mover handles both concatenations inside the sts-12, and to other sts-12s inside the core. the pointer mover block can correctly process any length of concatenation of sts frames (multiple of three) as long as it begins on an sts-3 boundary (i.e., sts-1 number one, four, seven, ten, etc.) and is contained within the smaller of sts-3, 12, or 48. see details in table 4. table 4. valid starting positions for an sts-mc note: yes = sts-mc spe can start in that sts-1. no = sts-mc spe cannot start in that sts-1. = yes or no, depending on the particular value of m. sts-1 number sts-3cspe sts-6cspe sts-9cspe sts-12cspe sts-15cspe sts-18c to sts-48c spes 1 yes yes yes yes yes yes 4 yes yes yes no yes 7 yes yes no no yes 10 yes no no no yes 13 yes yes yes yes yes 16 yes yes yes no yes 19 yes yes no no yes 22 yes no no no yes 25 yes yes yes yes yes 28 yes yes yes no yes 31 yes yes no no yes 34 yes no no no yes no 37 yes yes yes yes no no 40 yes yes yes no no no 43 yes yes no no no no 46 yes no no no no no
28 28 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) pointer interpreter state machine. the pointer inter- preters highest priority is to maintain accurate data flow (i.e., valid spe only) into the elastic store. this will ensure that any errors in the pointer value will be cor- rected by a standard, fully sonet compliant, pointer interpreter without any data hits. this means that error checking for increment, decrement, and new data flag (ndf) (i.e., 8 of 10) is maintained in order to ensure accurate data flow. a single valid pointer (i.e., 0782) that differs from the current pointer will be ignored. two consecutive incoming valid pointers that differ from the current pointer will cause a reset of the j1 location to the latest pointer value (the generator will then produce an ndf). this block is designed to handle single bit errors without affecting data flow or changing state. the pointer interpreter has only three states (norm, ais, and conc). norm state will begin whenever two consecutive norm pointers are received. if two con- secutive norm pointers that both differ from the cur- rent offset are received, then the current offset will be reset to the last received norm pointer. when the pointer interpreter changes its offset, it causes the pointer generator to receive a j1 value in a new posi- tion. when the pointer generator gets an unexpected j1, it resets its offset value to the new location and declares an ndf. the interpreter is only looking for two consecutive pointers that are different from the current value. these two consecutive norm pointers do not have to have the same value. for example, if the cur- rent pointer is ten and a norm pointer with offset of 15 and a second norm pointer with offset of 25 are received, then the interpreter will change the current pointer to 25. the receipt of two consecutive conc pointers causes conc state to be entered. once in this state, offset values from the head of the concate- nation chain are used to determine the location of the sts spe for each sts in the chain. two consecutive ais pointers cause the ais state to occur. any two con- secutive normal or concatenation pointers will end this ais state. this state will cause the data leaving the pointer generator to be overwritten with 0xff. 5-8589 (f) figure 10. pointer mover state machine pointer generator. the pointer generator maps the corresponding bytes into their appropriate location in the outgoing byte stream. the generator also creates offset pointers based on the location of the j1 byte as indicated by the pointer interpreter. the generator will signal ndfs when the interpreter signals that it is com- ing out of ais state. the pointer generator resets the pointer value and generates ndf every time a byte marked j1 is read from the elastic store that doesnt match the previous offset. increment and decrement signals from the pointer interpreter are latched once per frame on either the f1 or e2 byte times (depending on collisions); this ensures constant values during the h1 through h3 times. the choice of which byte time to do the latching on is made once when the relative frame phases (i.e., received and system) are determined. this latch point is then stable unless the relative framing changes and the received h byte times collide with the system f1 or e2 times, in which case the latch point would be switched to the col- lision-free byte time. there is no restriction on how many or how often incre- ments and decrements are processed. any received increment or decrement is immediately passed to the generator for implementation regardless of when the last pointer adjustment was made. the responsibility for meeting the sonet criteria for maximum frequency of pointer adjustments is left to an upstream pointer processor. when the interpreter signals an ais state, the genera- tor will immediately begin sending out 0xff in place of data and h1, h2, h3. this will continue until the inter- preter returns to norm or conc (pointer mover state machine) states and a j1 byte is received. norm conc ais 2 x c on c 2 x n o r m 2 x n or m 2 x a i s 2 x conc 2 x ais
lucent technologies inc. 29 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) transport overhead extraction transport overhead is extracted from the receive data stream by the toh extract block. the incoming data gets loaded into a 36-byte shift register on the system clock domain. this, in turn, is clocked onto the toh clock domain at the start of the spe time, where it can be clocked out. during the spe time, the receiver toh frame pulse is generated, rx_toh_fp, which indicates the start of the row of 36 toh bytes. this pulse, along with the receive toh clock enable, rx_toh_ck_en, as well as the toh data, are all launched on the rising edge of the toh clock toh_clk. toh byte ordering (backplane to fpga) the toh processor is responsible for dropping all toh bytes of each channel through one of four corresponding serial ports. the four toh serial ports are synchronized to the toh clock (the same clock that is being used by the serial ports on the transmitter side). this free-running toh clock is provided to the core by external circuitry and operates at a minimum frequency of 25 mhz and a maximum frequency of 77.76 mhz. data is transferred over serial links in a bursty fashion as controlled by the rx toh clock enable signal, which is generated by the asic and common to the four channels. all toh bytes of sts-12 streams are transferred over the appropriate serial link in the same order in which they appear in a standard sts-12 frame. data transfer should be preformed on a row-by- row basis such that internal data buffering needs is kept to a minimum. data transfers on the serial links will be synchronized relative to the rx toh frame signal. receiver toh reconstruction receiver toh reconstruction on output parallel bus is as shown in the following table (if the pointer mover is not bypassed). table 5. receiver toh (output parallel bus) on the toh serial port, all toh bytes are dropped as received on the lvds input (msb first). the only exception is the most significant bit of byte a1 of sts#1, which is replaced with an even parity bit. this parity bit is calculated over the previous toh frame. also, on ais-l (either resulting from lof or forced through software), all toh bits are forced to all ones with proper parity (parity we automatically ends up being set to 1 on ais-l). special toh byte functions k1 and k2 handling. the k1 and k2 bytes are used in automatic protection switch (aps) applications. k1 and k2 bytes can be optionally passed through the pointer mover under software control, or can be set to zero with the other toh bytes. a1 and a2 handling. as discussed previously, the a1 and a2 bytes are used for a framing header. a1 and a2 bytes are always regenerated and set to hexadecimal f6 and 28, respectively. a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 000000000000 k100000000000 k200000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 000000000000000000000000000000000000 regenerated bytes. regenerated bytes (under pointer generator control-ss bits must be transparent-ais-p must be supported). bytes taken from elastic store buffer, on negative stuff opportunity-else, forced to all zeros. transparent or all zeros (k1/k2 are either taken from k1/k2 buffer or forced to all zeros-soft, control). in transparent mode, ais-l must be supported. all zero bytes.
30 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) spe and c1j1 outputs . these two signals for each channel are passed to the fpga logic to allow a pointer pro- cessor or other function to extract payload without interpreting the pointers. for the ort8850, each frame has 12 sts-1s. in the spe region, there are 12 j1 pulses for each sts-1s. there is one c1(j0, new sonet specifica- tions use j0 instead of c1 as section trace to identify each sts-1 in an sts-n) pulse in the toh area for one frame. thus, there is a total of 12 j1 pulses and one c1(j0) pulse per frame. c1(j0) pulse is coincident with the j0 of sts1 #1. in each frame, the spe flag is active when the data stream is in spe area. spe behavior is dependent on pointer movement and concatenation. note that in the toh area, h3 can also carry valid data. when valid spe data is carried in this h3 slot, spe is high in this particular toh time slot. in the spe region, if there is no valid data during any spe column, the spe signal will be set to low. spe allow a pointer processor to extract payload without interpreting the pointers. the spe and c1j1 functionality are described in table 6. for generic data operation, valid data is available when spe is 1 and the c1j1 signal is ignored. table 6 . spe and c1j1 functionality note: the following rules are observed for generating spe and c1j1 signals: on occurrence of ais-p on any of the sts-1, there is no corre- sponding j1 pulse. in case of concatenated payloads (up to sts48c), only the head sts-1 of the group has an associated j1 pulse . c1j1 signal tracks any pointer movements. during a negative justification event, spe is set high during the h3 byte to indicate that payload data is available. during a positive justification event, spe is set low during the positive stuff opportunity byte to indicate that payload data is not available. 5-9330(f) note: c1j1 signal behavior shown in this figure is just for illustration purposes: c1 pulse position must always be as shown; ho wever, position of j1 pulses vary based on path overhead location of each sts-1 within the sts-12 stream. c1j1 signal must always be active during c1(j0) time slot of sts#1. c1j1 signal must also be active during the twelve j1 time slots. however, c1j1 must not be active for any sts-1 for which ais-p is gen- erated. also, on concatenated payloads, only the head of the group must have a j1 pulse. figure 11. spe and c1j1 functionality spe c1j1 descri p tion 0 0 toh information excludin g c1 ( j0 ) of sts1 #1. 0 1 position of c1 ( j0 ) of sts1 #1 ( one per frame ) . t y picall y used to provide a uni q ue link identification ( 256 possible uni q ue links ) to help ensure cards are connected into the backplane correctl y or cables are connected correctl y . 1 0 spe information excludin g the 12 j1 b y tes. 1 1 position of the 12 j1 b y tes. sts-12 toh row # 1 spe row # 1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a1 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 a2 j0 z0 z0 z0 z0 z0 z0 z0 z0 z0 z0 z0 sts-12 spe c1j1 c1 pulse j1 pulse of 3rd sts-1 1st spe bytes of the 12 sts-1s 123456789101112
preliminary data sheet september 2000 lucent technologies inc. 31 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc backplane transceiver core detailed description (continued) 5-9331 note: spe signal behavior shown in this figure is just for illustration purposes: spe behavior is dependent on pointer movements and concate- nation. spe signal must be high during negative stuff opportunity byte time slots (h3) for which valid data is carried (negative stuffi ng). spe signal must be low during positive stuff opportunity byte time slots for which there is no valid data (positive stuffing). figure 12. spe stuff bytes sts-12 toh row # 4 spe row # 4 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h1 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h2 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 h3 sts-12 spe positive stuff opportunity bytes 123456789101112 negative stuff opportunity bytes spe signal shows negative stuffing for 2nd sts-1, and positive stuffing for 6th sts-1 powerdown mode powerdown mode will be entered when the corre- sponding channel is disabled. channels can be inde- pendently enabled or disabled under software control. parallel data bus output enable and toh serial data output enable signals are made available to the fpga logic. the hsi macrocells corresponding channel is also powered down. the device will power up with all eight channels in powerdown mode. in addition, an lvds_en pin has been added to control the lvds pins during boundary scan. during functional operation, enabling/disabling lvds buffers is controlled by software registers. when in boundary scan mode, lvds_en controls the enabling/disabling of lvds buff- ers instead of software registers. this lvds_en pin should be pulled high on the board for functional opera- tion, and pulled low during boundary scan. redundancy and protection switching the ort8850 supports sts-12/sts-48 redundancy by either software or hardware control for protection switching applications. for the transmitter mode, no additional functionality is required for redundant opera- tion. for receiving data, sts-12 and sts-48 data redundancy can be implemented within the same device, while sts-192 and above data stream requires multiple ort8850 devices to support redundancy. in sts-12 mode, the channel a receive data bus port is used for both channel a and channel b. similarly, the channel c receive data bus port is used for both chan- nel c and channel d. channel b and channel d become the redundant channels. the channel b and channel d receive data bus ports are unused. soft reg- isters provide independent control to the protection switching muxes for both parallel data ports and serial toh data ports. when direct hardware control for pro- tection switching is needed, external protection switch pins are available for channels a and b, and also chan- nels c and d. the external protection switch pins only support parallel spe/toh data protection switching, but not the serial toh data. for sts-48 redundancy, the two 4-channel macro blocks are both used -4 channels for work and 4 chan- nels for protect. the switching between work and pro- tect is extended to either be between 4-channel macros or between the a/b and c/d channels within both mac- ros. in sts-192 mode, multiple independent devices are required to work and protect for redundancy. parallel and serial port output pins on the fpga side should be 3-stated as the basis for supporting redundancy. the existing local bus enable signals at the cic can be used as 3-state controls for fpga data bus if needed, which can be easily accessed by software control. users can also create their own protection switch 3- state enable signals either in fpga logic or external to the device, depending on the specific application.
32 32 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc rapidio interface to pi-sched overview the ort8850 includes three byte-wide full duplex ddr rapidio interfaces running at up to 311 mhz (622 mbits/s) per line for a total of 5.0 gbits/s for each interface. each input and output interface includes byte-wide data, one control signal (such as start-of- cell), and one clock signal. one of the three rapidio interfaces is always available. the other two rapidio interface are available only if the eight cdr channels are not being used. one function of the ort8850 is to interface with the protocol independent scheduler (pi-sched) device on a port card. the pi-sched ic is part of the high-speed switching (hssw) family of devices. it offers a highly- integrated, innovative, and complete vlsi solution for implementing the scheduling and buffer management functionality of a cell (e.g., atm) or packet (e.g., ip) switching system port at oc-48c. the rapidio in the ort8850 will support the dedi- cated receive and transmit interfaces for off-chip com- munication. both interfaces drive or receive off-chip through lvds i/o pads. the lvds i/os are fully termi- nated on-chip to allow for driving high-speed parallel backplanes at speeds up to 311 mhz. internally, each 8-bit rapidio interface is connected to a 32-bit inter- face which is single-edge clocked and connected to the fpga logic array. for example, byte-wide 311 mhz ddr data is converted to 155 mhz 32-bit wide data at the fpga interface. the primary task of the rapidio is to process bytes of data known as octets transmitted as a group known as a cell. an octet is described as 8 bits found within a cell. once the first octet of a cell is received, subse- quent octets are part of an uninterrupted data stream until the entire cell has been received. the beginning of the next cell will determine the boundary of the previ- ous cell. the beginning of a cell is indicated by a pulse on the start-of-cell, soc signal. the soc signal always accompanies the cell data. at the i/o boundary, cell data is present on an 8-bit data bus with the first octet and soc aligned with the rising edge of the clock. at the fpga end, cell data is present on a 32-bit data bus. thus the rapidio is used to translate between the 32-bit data bus and the 8-bit i/o data bus while moni- toring the integrity of the cells being processed. receive cell interface the receive interface performs de-multiplexing from 4 sequential octets of 8 pairs of lvds pins using both edges of the high-speed clock onto internal 32-bit bus- ses at the low speed clock. the interface includes the following signals (see figure 13): n one lvds clock pair running at 120 -311 mhz. its relationship is intended to be in the eye of the receive cell data. n one lvds start-of-cell pair which indicates that word 0 of a data cell is on the receive data port. n eight lvds data pairs, double edge clocked by the lv d s c l o c k . the eight lvds data pairs are double-edge clocked by the lvds receive clock (rxclk). the rxclk is aligned to the center of the eye of the received data and start-of-cell (rxd and rxsoc). to achieve opti- mal timing margin, the receiver is required to maintain this alignment. the rapidio interface requires that the soc spacing is an integer multiple of two clock cycles for proper operation and that socs occur only on the rising edge of the receive clock (rxclk).
lucent technologies inc. 33 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc rapidio interface to pi-sched (continued) 0676 figure 13. rapidio receive cell interface octets and start of cell cells will be transmitted on the high-speed lvds inputs as octets. the first octet o0 (consisting of d0_0, d1_0...d7_0) will be present on bits 31:24 on the low-speed 32-bit fpga bus. similarly, octet o1 (consisting of d0_1, 1_1... d7_1) will be present on bits 23:16 on the 32-bit bus. thus, octets will always be transmitted from 1st octet to last. the minimum number of octets present on the high-speed ports should always be divisible by 4, evenly representing the relationship with the 32-bit core of the asic interface. the start-of-cell signal is always aligned with the first octet of each cell. once the first octet of a cell is received, subsequent octets are part of an uninterrupted data stream until the entire cell has been received. the number of octets in a cell is determined by the register bits ocellsize. the rapidio can support varying minimum cell sizes from 4 octets up to 124 in increments of 4. the rapidio is programmed with the cell size by writing to the ocellsize register via the micro- processor interface. if the transmitted cell size is less than the programmed cell size, a violation occurs and the irxsocviol flag is active. this flag can be ignored if a given minimum cell size is not needed. d clk q rxclk rxsoc d ck q zrxd_7 zrxd_23 zrxd_31 zrxd_15 wrxclk (133 mhz) to fpga 133 mhz clock domain 266 mhz clock domain input repeated 7 times (one for each of rxd[1:7]) dq zrxsoc dq dq dq rxd[7] rxd[0] zrxd_15 d clk q data capture shift registers d ck q d ck q d ck q d ck q d ck q d ck q d ck q d ck q
34 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc rapidio interface to pi-sched (continued) 0677 figure 14. rapidio transmit cell interface transmit cell interface the transmit interface performs multiplexing of 32 bits of low-speed data onto 4 sequential octets of 8 pairs of lvds signal pins using both edges of a high-speed clock. the transmitter module consists of the following 10 lvds sig- nal pairs (see figure 14): n eight lvds data pairs (txd) double edge clocked by the lvds clock txclk. the data pairs carry biphase data at 120-311 mhz. n one start-of-cell lvds pair that indicates that octet 0 of a data cell is on txd. the transitions of this signal are at 90 degrees also with the crossing points of the lvds clock (txclk). n one lvds clock pair output txclk operating at 120 to 311 mhz. its relationship is intended to be exactly in 90 degree phase with the transitions of txd data and txsoc. the high-speed data outputs (txd[0:7]) as well as the start-of-cell signal txsoc are generated as a result of the positive edge of pfclk. this is accomplished by multiplexing between the even and odd bytes of the data at a 1/2 pfclk rate. pfclk is derived from the internal pll and operates at 4x the base frequency or between 240 mhz and 284 mhz. the pfclk is expected to have a duty cycle of 47% to 53% with no more than 150 ps of jitter. the duty cycle of pfclk will directly affect the accuracy of the high speed clock and its ability to maintain the eye of the data. the 90 degree phase shift of the output clock puts txclk in the eye of the data. common transmit fifo even byte odd byte even byte utxd [31:0] utxsoc wutxclk (60 mhz146 mhz) output port clock alignment mux output port soc alignment mux fpga i/f pfclk (4x output clock from pll) 32 to 8 input soc register soc txsoc (240 mhz584 mhz) off-chip interface pll positive- output port data alignment muxes mux controller txclk txd[7:0] odd byte output port data alignment muxes edge flops negative- edge flops
lucent technologies inc. 35 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc rapidio interface to pi-sched (continued) table 7. rapidio signals to/from fpga interface name (all end with _a, _b, or _c depending on channel) from fpga to fpga description receive cell interface zrxd<31:0> 32 32-bit data from the receive module. the bus contains 4 octets and reflects data received via the high-speed rxd data bus. zrxsoc 1 indicates the presence of the 1st octet of a new cell within the first 32-bit data word on the bus rxd in bit positions [31:24]. zrxsocviol 1 indicates a minimum cell violation within the receive module. this signal will transition active high coincident with rxsoc. an active state signals the new cell overran the previous cell and the previous cell is in violation of the minimum cell size. zrxalnviol 1 signals an alignment error. an active state signals rxsoc was captured on a negative rxclk edge. the violation condition on this signal will stay high for a single wrxclk_[chan]_fpga cycle coincident with rxsoc. zclkstat indicates the loss or absence of a clock on the lvds clock (rxclk). this signal will be present for the duration of the absence of the clock, following a period to validate its absence. csysenb 1 system cell processing enable. after reset is released, drive this signal high when the rapidio is ready to transmit cells. this signal should be active after all control signals into the rapidio are stable. rstn_rx 1 synchronous reset for all memory elements clocked by wrxclk_[chan]_fpga (derived from pll) wrxclk_[chan]_fpga 1 derived from high speed lvds clock rxclk (rxclk/2). transmit cell interface utxd[31:0] 32 transmit data bs containing 4 octets synchronized with the ris- ing edge of the 60 mhz146 mhz wutxclk_fpga (derived from pll) is clocked into the transmit fifo within the rapidio . utxsoc 1 start of cell, originating within core, synchronized with the ris- ing edge of wutxclk_fpga into the transmit fifo. indicates the first data word on txd bus includes the first octet of a new cell in bit positions [31:24]. rstn_utx 1 synchronous reset for all memory elements in the wutxclk domain. utxtristn 1 output 3-state enable (active-low). when active, the txd, txsoc and txclk lvds drivers are 3-stated. 0 - 3-state txd, txsoc and txclk drivers. 1 - normal operation. fpga interface clocks (common to all channels) wutxclk_fpga 1 one x core clock generated from an internal pll circuit. syn- chronous to utxd and utxsoc data inputs. halfclk_fpga 1 1/2 x main pll output clock. phase aligned with pfclk. nom- inal frequency = 30 mhz to 73 mhz. duty cycle spec = 47%/ 53%.
36 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc rapidio interface to pi-sched (continued) table 8. signals used as register bits memory map definition of register types there are six structural register elements: sreg, creg, preg, iareg, isreg, and iereg. there are no mixed registers in the chip. this means that all bits of a particular register (particular address) are structurally the same. all of these registers are accessed via the fpga system bus which in turn can be accessed by the mpi block or through fpga logic. register bit(s) description oshlbenb used during the internal built-in-self-test mode. indicates that the single-ended versions of the transmit module outputs should be looped back into the single ended inputs of the receive module. oshlenb = 0 : no loopback. oshlenb = 1 : loopback. ocellsize[4:0] this value indicates the minimum cell size and will be used to detect cell under-run errors. this value should be set and stable prior to initialization of operation and stable thereafter. otestenb enables the internal self test of the rapidio block. two loopback paths exist during test, inter- nal and external. during both tests, data is passed through all modules and verified. itestdone indicates the completion of the internal test. only valid during a test when otestenb is high. itestdone = 0 test running. itestdone = 1 test complete. itestpass indicates the success of the internal test. this signal is valid only when itestdone is high. itestpass = 0 test failed. itestpass = 1 test passed. tristn active-low. 3-state override for transmit outputs. this signal is ignored during reset, but takes priority over all 3-state control signals when active.
lucent technologies inc. 37 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 9. structural register elements registers access and general description the memory map comprises three address blocks: n generic register block: id, revision, scratch pad, lock, fifo alignment, and reset registers. n device register block: control and status bits, common to the four channels in each of the two quad interfaces. n channel register blocks: each of the four channels in both quads have an address block. the four address blocks in both quads have the same structure, with a constant address offset between channel register blocks. all registers are write-protected by the lock register, except for the scratch pad register. the lock register is a 16-bit read/write register. write access is given to registers only when the key value 0xa001 is present in the lock regis- ter. an error flag will be set upon detecting a write access when write permission is denied. the default value is 0x0000. after powerup reset or soft reset, unused register bits will be read as zeros. unused address locations are also read as zeros. write only register bits will be read as zeros. the detailed information on register access and func- tion are described on the tables, memory map, and memory map bit description. a full memory map is included in table 10, followed by detailed descriptions in table 11. element register description sre g status re g ister a status re g ister is read onl y , and, as the name implies, is used to conve y the status information of a particular element or function of the ort8850 core. the reset value of an sre g is reall y the reset value of the particular element or function that is bein g read. in some cases, an sre g is reall y a fixed value. an example of which is the fixed id and revision re g isters. cre g control re g ister a control re g ister is read and writable memor y element inside core control. the value of a cre g will alwa y s be the value written to it. events inside the ort8850 core cannot effect cre g value. the onl y exception is a soft reset, in which case the cre g will return to its default value. pre g pulse re g ister each element, or bit, of a pulse re g ister is a control or event si g nal that is asserted and then deasserted when a value of one is written to it. this means that each bit is alwa y s of value 0 until it is written to, upon which it is pulsed to the value of one and then returned to a value of 0. a pulse re g ister will alwa y s have a read value of 0. iare g interrupt alarm re g ister each bit of an interrupt alarm re g ister is an event latch. when a particular event is pro- duced in the ort8850 core, its occurrence is latched b y its associated iare g bit. to clear a particular iare g bit, a value of one must be written to it. in the ort8850 core, all isre g reset values are 0. isre g interrupt status re g ister each bit of an interrupt status re g ister is ph y sicall y the lo g ical-or function. it is a con- solidation of lower level interrupt alarms and/or isre g bits from other re g isters. a direct result of the fact that each bit of the isre g is a lo g ical-or function means that it will have a read value of one if an y of the consolidation si g nals are of value one, and will be of value 0 if and onl y if all consolidation si g nals are of value 0. in the ort8850 core, all isre g default values are 0. ere g interrupt enable re g ister each bit of a status re g ister or alarm re g ister has an associated enable bit. if this bit is set to value one, then the event is allowed to propa g ate to the next hi g her level of con- solidation. if this bit is set to zero, then the associated iare g or isre g bit can still be asserted but an alarm will not propa g ate to the next hi g her level. an interrupt enable bit is an interrupt mask bit when it is set to value 0.
38 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) memory map overview table 10 . memory map addr [6:0] reg. type db7 db6 db5 db4 db3 db2 db1 db0 default value (hex) notes generic register block 00 sreg fixed rev [7:0] 01 1 01 sreg fixed id lsb [7:0] 01 02 sreg fixed id msb [7:0] a0 03 creg scratch pad [7:0] 00 04 creg lockreg msb [7:0] 00 05 creg lockreg lsb [7:0] 00 06preg fifo alignment command global reset com- mand na device register block 08 creg rx toh frame and rx toh clock enable control ext prot sw en ext prot sw function sts-48 sts-12 sel lv d s lpbk control 00 2 09 creg parallel port out- put mux select for ch c parallel port out- put mux select for ch a serial port output mux select for ch c serial port out- put mux select for ch a 0f 0a creg fifo aligner threshold value (min) [4:0] 02 0b creg fifo aligner threshold value (max) [4:0] 15 0c creg scram- bler/ descram- bler control input/ output parallel bus par- ity con- trol line loop- back control number of consecutive a1/a2 errors to generate [3:0] 60 3 0d creg a1 error insert value [7:0] 00 0e creg a2 error insert value [7:0] 00 0f creg transmitter b1 error insert mask [7:0] 00
lucent technologies inc. 39 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 10. memory map (continued) addr [7:0] register type register name db7 db6 db5 db4 db3 db2 db1 db0 reset value (hex) comments 00 sreg ds_1_sreg, all_spif_re gsel [0] fixed rev [7:0] 01 generic register block 01 sreg ds_2_sreg, all_spif_re gsel [1] fixed id lsb [7:0] 01 02 sreg ds_3_sreg, all_spif_re gsel [2] fixed id msb [7:0] a0 03 creg dl_1_creg, lock_regsel [0] scratch pad [7:0] 00 04 creg dl_2_creg, ock_regsel [1] lockreg msb [7:0] 00 05 creg dl_3_creg, ock_regsel [2] lockreg lsb [7:0] 00 06 preg global reset comm and n.a. device register block 08 creg ds_4_creg, all_spif_re gsel [3] rx toh frame and rx toh clk enable hiz control ext prot sw en ext prot sw func lvds lpbk control 00 device reg. blk - rx 09 creg ds_5_creg, all_spif_re gsel [4] parallel port output mux select for ch#7 parallel port output mux select for ch#5 serial port output mux select for ch#7 serial port output mux select for ch#5 parallel port output mux select for ch#3 parallel port output mux select for ch#1 serial port output mux select for ch#3 serial port output mux select for ch#1 ff (4 ch was 0f) 0a creg ds_6_creg, all_spif_re gsel [5] fifo aligner threshold value (min) [4:0] 02 0b creg ds_7_creg, all_spif_re gsel [6] fifo aligner threshold value (max) [4:0] 15
40 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 10. memory map (continued) addr [7:0] register type register name db7 db6 db5 db4 db3 db2 db1 db0 reset value (hex) comments 0c creg ds_8_creg, all_spif_re gsel [7] scram bler/ descra mbler control input/ output parallel bus parity control line lpbk control number of consecutive a1 a2 errors to generate [3:0] 60 device reg blk - tx 0d creg ds_9_creg, all_spif_re gsel [8] a1 error insert value [7:0] 00 0e creg ds_10_cre g, all_spif_re gsel [9] a2 error insert value [7:0] 00 0f creg ds_11_cre g, all_spif_re gsel [10] transmitter b1 error insert mask [7:0] 00 10 isreg ds_12_isr, all_spif_re gsel [11] per device int ch 4 int ch 3 int ch 2 int ch 1 int 00 top level interrupts 11 iereg ds_13_ier, all_spif_re gsel [12] enable/mask register [4:0] 00 12 iareg ds_14_iar, all_spif_re gsel [13] write to locked registe r error flag frame offset error flag 00 13 iereg ds_15_ier, all_spif_re gsel [14] enable/mask register [1:0] 00 14 isreg ds_16_isr, all_spif_re gsel [159] ch 8 int ch 7 int ch 6 int ch 5 int 00 15 iereg ds_17_ier, all_spif_re gsel [160] enable/mask register [3:0] 00 16 creg stm-a mode control stm-a mode control stm-b mode control stm-b mode control 0x00
lucent technologies inc. 41 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 10. memory map (continued) addr [7:0] register type register name db7 db6 db5 db4 db3 db2 db1 db0 reset value (hex) comments 17 creg stm a stream a resync. stm a stream b resync stm a stream c resync stm a stream d resync stm b stream a resync stm b stream b resync stm b stream c resync stm b stream d resync 0x00 18 creg stm a and b resync (all 8 stream s aa to bd) stm a resyn c (all 4 stream s aa, ab, ac and ad) stm b resyn c (all 4 stream s ba, bb, bc and bd) twins aa resyn c (strea ms aa and ba) twins bb resync (strea ms ab and bb) twins cc resync (strea ms ac and bc) twins dd resync (strea ms ad and bd) 0x00 channel register block 20, 38, 50, 68, 80, 98, b0, c8 creg dsbr_1_1/ 2/3/4_creg all_spif_re gsel[15, 33, 51, 69 hi-z control of toh data output hi-z control of parallel output bus chann el enable / disable control parallel output bus parity err ins cmd rx k1/ k2 source select toh serial output port par err ins cmd force ais-l control rx behavi or in lof 01 rx control signals 21, 39, 51, 69, 81, 99, b1, c9 creg dsbr_2_1/ 2/3/4_creg all_spif_re gsel[16, 34, 52, 70 tx mode of operati on tx e1 f1 e2 source select tx s1 m0 source select tx k1 k2 source select tx d12 source select tx d11 source select tx d10 source select tx d9 source select 00 tx control signals 22, 3a, 52, 6a, 82, 9a, b2, ca creg dsbr_3_1/ 2/3/4_creg all_spif_re gsel[17, 35, 53, 71 tx d8 source select tx d7 source select tx d6 source select tx d5 source select tx d4 source select tx d3 source select tx d2 source select tx d1 source select 00 23, 3b, 53, 6b, 83, 9b, b3, cb creg dsbr_4_1/ 2/3/4_creg all_spif_re gsel[18, 36, 54, 72 disable a1/a2 insert disable b1 insert b1 error insert comm and a1 a2 error ins comm and 00
42 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 10. memory map (continued) addr [7:0] register type register name db7 db6 db5 db4 db3 db2 db1 db0 reset value (hex) comments 24, 3c, 54, 6c, 84, 9c, b4, cc sreg dsbr_5_1/ 2/3/4_sreg all_spif_re gsel[19, 37, 55, 73 concat indicati on 12 concat indicati on 9 concat indicati on 6 concat indicati on 3 n.a. per sts#1 cos flag 25, 3d, 55, 6d, 85, 9d, b5, cd sreg dsbr_6_1/ 2/3/4_sreg all_spif_re gsel[20, 38, 56, 74 concat indicati on 11 concat indicati on 8 concat indicati on 5 concat indicati on 2 concat indicati on 10 concat indicati on 7 concat indicati on 4 concat indicati on 1 n.a. 26, 3e, 56, 6e, 86, 9e, b6, ce isreg dsbr_7_1/ 2/3/4_isr all_spif_re gsel[21, 39, 57,75 elastic store overflo w flag ais-p flag per sts-12 alarm flag 00 per channel interrupt consolidation 27, 3f, 57, 6f, 87, 9f, b7, cf iereg dsbr_8_1/ 2/3/4_ier all_spif_re gsel[22, 40, 58, 76, 94 enable/mask register [2:0] 00 28, 40, 58, 70, 88, a0, b8, d0 iareg dsbr_9_[1: 8]_iar all_spif_re gsel[23, 41, 59, ... fifo oos error flag toh serial input port parity error flag input parallel bus parity error flag lvds link b1 parity error flag lof flag receiv er interna l path parity error flag fifo aligner thresh old error flag 00 per sts-12 interrupt flags 29, 41, 59, 71, 89, a1 b9, d1 iereg dsbr_10_1/ 2/3/4_ier all_spif_re gsel[24, 42, 60, enable/mask register [5:0] 00
lucent technologies inc. 43 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 10. memory map (continued) addr [7:0] register type register name db7 db6 db5 db4 db3 db2 db1 db0 reset value (hex) comments 2a, 42, 5a, 72, 8a, a2, ba, d2 iareg dsbr_11_1/ 2/3/4_iar all_spif_re gsel[25, 43, 61, ais interru pt flags 12 ais interru pt flag 9 ais interru pt flags 6 ais interru pt flags 3 00 per sts-1 interrupt flags 2b, 43, 5b, 73, 8b, a3, bb, d3 iareg dsbr_12_1/ 2/3/4_iar all_spif_re gsel[26, 44, 62, ais interru pt flag 11 ais interru pt flag 8 ais interru pt flag 5 ais interru pt flag 2 ais interru pt flag 10 ais interru pt flag 7 ais interru pt flag 4 ais interru pt flag 1 00 2c, 44, 5c, 74, 8c, a4, bc, d4 iereg dsbr_13_1/ 2/3/4_ier all_spif_re gsel[27, 45, 63, enable /mask ais interru pt flags 12 enable /mask ais interru pt flag 9 enable /mask ais interru pt flags 6 enable /mask ais interru pt flags 3 00 2d, 45, 5d, 75, 8d, a5, bd, d5 iereg dsbr_14_1/ 2/3/4_ier all_spif_re gsel[28, 46, 64, enable /mask ais interru pt flag 11 enable /mask ais interru pt flag 8 enable /mask ais interru pt flag 5 enable /mask ais interru pt flag 2 enable /mask ais interru pt flag 10 enable /mask ais interru pt flag 7 enable /mask ais interru pt flag 4 enable /mask ais interru pt flag 1 00 2e, 46, 5e, 76, 8e, a6, be, d6 iareg dsbr_15_1/ 2/3/4_iar all_spif_re gsel[29, 47, 65, es overflo w flags 12 es overflo w flag 9 es overflo w flags 6 es overflo w flags 3 00 2f, 47, 5f, 77, 8f, a7, bf, d7 iareg dsbr_16_1/ 2/3/4_iar all_spif_re gsel[30, 48, 66, es overflo w flag 11 es overflo w flag 8 es overflo w flag 5 es overflo w flag 2 es overflo w flag 10 es overflo w flag 7 es overflo w flag 4 es overflo w flag 1 00
44 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 10. memory map (continued) addr [7:0] register type register name db7 db6 db5 db4 db3 db2 db1 db0 reset value (hex) comments 30, 48, 60, 78, 90, a8, c0, d8 iereg dsbr_17_1/ 2/3/4_ier all_spif_re gsel[31, 49, 67, enable /mask es overflo w flags 12 enable /mask es overflo w flag 9 enable /mask es overflo w flags 6 enable /mask es overflo w flags 3 00 31, 49, 61, 79, 91, a9, c1, d9 iereg dsbr_18_1/ 2/3/4_ier all_spif_re gsel[32, 50, 68, enable /mask es overflo w flag 11 enable /mask es overflo w flag 8 enable /mask es overflo w flag 5 enable /mask es overflo w flag 2 enable /mask es overflo w flag 10 enable /mask es overflo w flag 7 enable /mask es overflo w flag 4 enable /mask es overflo w flag 1 00 32, 4a, 62, 7a, 92, aa, c2, da counter null_re gsel[0, 3, 6, 9, 12, 15, 18, 21] overflo w lvds link b1 bip-8 parity error counter 00 binning 33, 4b, 63, 7b, 93, ab, c3, db counter null_re gsel[1, 4, 7, 10, 13, 16, 19, 22] overflo w lof counter 00 34, 4c, 64, 7c, 94, ac, c4, dc counter null_re gsel[2, 5, 8, 11, 14, 17, 20, 23] overflo w a1 a2 frame error counter 00 35, 4d, 65, 7d, 95, ad, c5, dd creg reserv ed fifo depth register 0x0c
lucent technologies inc. 45 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 10. memory map (continued) addr [7:0] register type register name db7 db6 db5 db4 db3 db2 db1 db0 reset value (hex) comments 36, 4e, 66, 7e, 96, ae, c6, de counter sampler phase error count 0x00 37, 4f, 67, 7f, 97, af, c7, df creg framer disabl e sync control lvds redund ant select bypas s alignm ent fifo + pointer mover bypas s alignm ent fifo only 0x00 cdr specific registers e0 creg cdr_ctl_reg 1 tstm ode bypa ss loop bken tstp hase x4int fce en10b it shim mode e1 creg cdr_ctl_reg 2 halfrate[7:0] 0x0 is this needed? e2 creg cdr_ctl_reg 3 quartrate[7:0] 0x0 is this needed? e3 creg cdr_ctl_reg 4 encomma[7:0] pi-sched registers f0 creg pi_ctl_reg1 oshl benb opim ode (reser ved) ocellsize[4:0] f1 sreg pi_stat_reg 1 itest done itest pass 0x0 f2 creg pi_ctl_reg2 ibypa ss otes tenb f3 creg pll_ctl_reg 1 opllt[5:0] opllt lfb opllt man 0x0 test control signals for pll
46 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 11. memory map descriptions bit/register name(s) bit/register location (hex) register type reset value (hex) description fixed rev [7:0] fixed id lsb [7:0] fixed id msb [7:0] 00 [7:0] 01 [7:0] 02 [7:0] sreg 01 01 a0 n.a. scratch pad [7:0] 03 [7:0] creg 00 the scratch pad has no function and is not used anywhere in the ort4622 core. however, this regi ster can be written to and read from. lockreg msb [7:0] lockreg lsb [7:0] 04 [7:0] 05 [7:0] creg 00 00 in order to write to registers in memory locations 06~7f, lockreg msb and lockreg lsb must be respectively set to the values of a0 and 01. if the msb and lsb lockreg values are not set to {a0, 01}, then any values written to the registers in memory locations 06~7f will be ignored. after reset (both hard and soft) the ort4622 core is in a write locked mode. the ort4622 core needs to be unlocked before it can be written to. also note that the scratch pad register (03) can always be written to as it is unaffected by write lock mode. global reset command 06 [0] preg n.a. the global reset command is accessed via the pulse register in memory address 06. the global reset command is a soft (software initiated) reset. nevertheless, the global reset command will have the exact reset effect as a hard (rst_n pin) reset. device register blocks lvds lpbk control 08 [0] creg 0 sts 48 sts12 sel 08 [1] creg 0 this control signal is unused in the ort4622 core. it is a scratch bit, and its value has no effect on the ort4622 core. ext prot sw en ext prot sw func 08 [3:2] creg 0 rx toh frame and rx toh clk enable hiz control 08 [4] creg 0 0 no loop back 1 lvds loop back, transmit to receive on ext port sw en ext prot sw func switching control master 0- - mux is controlled by software (1 control bit per mux) reg 09 . - output buffers enables are controlled by software (1 control bit per channel) reg 20, 38, 50, 68. 10 - mux on parallel output bus of channel #1 is controlled by prot_switch a/b pin (0 -> channel #1, 1-> channel #2). - mux on parallel output bus of channel #3 is controlled by prot_switch c/d pin (0 -> channel #3, 1-> channel #4). - output buffers enables are controlled by software (1 control bit per channel) reg 20, 38, 50, 68. 11 - mux is controlled by software (1 control bit per mux) reg 09 . - parallel output enable douta_en of channels #1 and doutb_en of chennel #2 are controlled by prot_switch a/b pin (0 -> en=1, 1-> en=0). - parallel output enable doutc_en of channels #3 and doutd_en of channel #4 are controlled by prot_switch c/d pin (0 -> en=1, 1-> en=0). note: ext prot sw func =0 in oc12 mode 0 toh_ck_fp_en=0, can be used to tri-state rx_toh_ck_en and rx_toh_fp signals. 1 function mode.
lucent technologies inc. 47 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 11. memory map descriptions (continued) bit/register name(s) bit/register location (hex) register type reset value (hex) description serial port output mux select for ch#1 serial port output mux select for ch#3 parallel port output mux select for ch#1 parallel port output mux select for ch#3 09 [0] 09 [1] 09 [2] 09 [3] creg 1 1 1 1 fifo aligner threshold value (min) [4:0] fifo aligner threshold value (max) [4:0] 0a [4:0] 0b [4:0] creg 02 15 these are the minimum and maximum thresholds values for the per channel receive direction alignment fifos. if and when the minimum or maximum threshold value is violated by a particular channel, then the interrupt event fifo aligner threshold error will be generated for that channel and latched as a fifo aligner threshold error flag in the respective per sts-12 interrupt alarm register. the allowable range for minimum threshold values is 1 to 23 the allowable range for maximum threshold values is 0 to 22 note that the minimum and maximum fifo aligner threshold values apply to all 4 channels. number of consecutive a1 a2 errors to generate [3:0] a1 error insert value [7:0] a2 error insert value [7:0] 0c [3:0] 0d [7:0] 0e [7:0] creg 00 00 00 these 3 per device control signals are used in conjunction with the per channel a1 a2 error insert command control bits to force a1 a2 errors in the transmit direction. if a particular channels a1 a2 error insert command control bit is set to the value 1 then the a1 and a2 error insert values will be inserted into that channels respective a1 and a2 bytes. the number of consecutive frames to be corrupted is determined by the number of consecutive a1 a2 errors to generate[3:0] control bits. the error insertion is based on a rising edge detector. as such the control must be set to value 0 before trying to initiate a second a1 a2 corruption. line lpbk control 0c [4] creg 0 input/output parallel bus parity control 0c [5] creg 1 scrambler/ descrambler control 0c [6] creg 1 transmit b1 error insert mask [7:0] 0f [7:0] creg 00 ch 1 int ch 2 int ch 3 int ch 4 int per device int enable/mask register for ch 1-4 + device[4:0] ch 5 int ch 6 int ch 7 int ch 8 int enable/mask register for ch5-8 [3:0] 10 [0] 10 [1] 10 [2] 10 [3] 10 [4] 11 [4:0] 14 [0] 14 [1] 14 [2] 14 [3] 15 [3:0] isreg isreg isreg isreg isreg iereg isreg isreg isreg isreg iereg 0 0 0 0 0 0 0 0 0 0 0 consolidation interrupts. 1 = interrupt, 0 = no interrupt. serial port output mux select for ch #1 0 toh output #1 is multiplexed to channel 2 1 toh output #1 is multiplexed to channel 1 serial port output mux select for ch #3 0 toh output #3 is multiplexed to channel 4 1 toh output #3 is multiplexed to channel 3 parallel port output mux select for ch #1 0 parallel output data bus #1 is multiplexed to channel 2 1 parallel output data bus #1 is multiplexed to channel 1 parallel port output mux select for ch #3 0 parallel output data bus #3 is multiplexed to channel 4 1 parallel output data bus #3 is multiplexed to channel 3 0 no loop back 1 rx to tx loopback on line side 0 even parity 1 odd parity 0 no rx direction descramble / tx direction scramble 1 in rx direction descramble channel after sonet frame recovery. in tx direction scramble data just before parallel to serial conversion. 0 no error insertion 1 invert corresponding bit in b1 byte
48 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 11. memory map descriptions (continued) bit/register name(s) bit/register location (hex) register type reset value (hex) description frame offset error flag write to locked register error flag enable/mask register [1:0] 12 [0] 12 [1] 13 [1:0] iareg iareg iereg 0 0 0 if in the receive direction the phase offset between any 2 channels exceeds 17 bytes, then a frame offset error event will be issued. this condition is continuously monitored. if the ort4622 core memory map has not been unlocked (by writing a 001 to the lock registers), and any address other than the lockreg registers or scratch pad register is written to, then a write to locked register event will be generated stm a mode control stm b mode control 16[3:2] 16[1:0] creg creg 0 0 00 - quad sts-12 or sts-48 01 - quad sts-3 10 - quad sts-1 00 - quad sts-12 or sts-48 01 - quad sts-3 10 - quad sts-1 individual alignment resync register 17[7:0] creg 0 write 1 to resync group alignment resync register 18[7:0] creg 0 write 1 to resync channel register blocks rx behavior in lof force ais-l control 20, 38, 50, 68, 80, 98, b0, c8 [0] 20, 38, 50, 68, 80, 98, b0, c8 [1] 1 0 toh serial output port par err ins cmd 20, 38, 50, 68, 80, 98, b0, c8 [2] 0 rx k1/k2 source select 20, 38, 50, 68, 80, 98, b0, c8 [3] 0 parallel output bus parity err ins cmd 20, 38, 50, 68, 80, 98, b0, c8 [4] 0 channel enable / disable control hi-z control of parallel output bus hi-z control of toh data output 20,,38,,50,,68, 80, 98, b0, c8 [5] 20, 38, 50, 68, 80, 98, b0, c8 [6] 20, 38, 50, 68, 80, 98, b0, c8 [7] creg creg creg 0 0 0 rx behavior in log 0 when rx direction oof occurs, do not insert ais-l 1 when rx direction oof occurs, insert ais-l force ais-l control 0 do not force ais-l 1 force ais-l 0 do not insert a parity error 1 insert parity error in parity bit of receive toh serial output for as long as this bit is set 0 set receive direction k2 k2 bytes to 0 1 pass receive direction k1 k2 though pointer mover 0 do not insert parity error 1 insert parity error in the parity bit of receive direction parallel output bus for as long as this bit is set channel enable / disable control 0 power down cdr channels (pwr_dn_a/b/c/d_n=0). toh_en_a(or b, c, d)=0, and douta(or b, c, d)=0, can be used to tristate output busses 1 functional mode hi-z control of parallel output bus 0 douta(or b, c, d) _en=0, can be used to tristate output bus 1 functional mode hi-z control of toh data output 0 toh_en_a(or b, c, d)=0, can be used to tristate toh output lines 1 funct i onal mode
lucent technologies inc. 49 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 11. memory map descriptions (continued) bit/register name(s) bit/register location (hex) register type reset value (hex) description tx mode of operation tx e1 f2 e2 source select tx s1 m0 source select tx k1 k2 source select tx d12~d9 source select tx d8~d1 source select 21,39,51,69, 81,99,b1,c9 [7] 21,39,51,69, 81,99,b1,c9 [6] 21,39,51,69, 81,99,b1,c9 [5] 21,39,51,69, 81,99,b1,c9 [4] 21,39,51,69, 81,99,b1,c9 [3:0] 22, 3a, 52, 6a, 82, 9a, b2, ca [7:0] creg creg creg creg creg creg 0 0 0 0 4h0 8h00 a1 a2 error insert command b1 error insert command disable b1 insert disable a1 insert 23, 3b, 53, 6b, 83, 9b, b3, cb [0] 23, 3b, 53, 6b, 83, 9b, b3, cb [1] 23, 3b, 53, 6b, 83, 9b, b3, cb[2] 23, 3b, 53, 6b, 83, 9b, b3, cb[3] creg creg 0 0 concat indication 12, 9, 6, 3 concat indication 11, 8, 5, 2, 10, 7, 4, 1 24, 3c, 54, 6c, 84, 9c, b4, cc [3:0] 25, 3d, 55, 6d, 85, 9d, b5, cd [7:0] sreg sreg 0 0 the value 1 in any bit location indicates that sts# is in concat mode. a 0 indicates that the sts in not in concat mode, or is the head of a concat group. per sts-12 alarm flag ais-p flag elastic store overflow flag enable/mask register [2:0] 26,3e,56,6e, 86,9e,b6,ce[0] 26, 3e, 56, 6e, 86,9e,b6,ce [1] 26,3e,56,6e, 86,9e,b6,ce [2] 27, 3f, 57, 6f, 87,9f, b7, cf [2:0] isreg isreg isreg iereg 0 0 0 3b000 these flag register bits per sts-12 alarm flag, ais-p flag, and elastic store overflow flag are the per channel interrupt status (consolidation) register. fifo aligner threshold error flag receiver internal path parity error flag lof flag lvds link b1 parity error flag input parallel bus parity error flag toh serial input port parity error flag fifo oos error flag enable/mask register [5:0] 28, 40, 58, 70, 88, a0, b8, d0 [0] 28, 40, 58, 70, 88, a0, b8, d0 [1] 28, 40, 58, 70, 88, a0, b8, d0 [2] 28, 40, 58, 70, 88, a0, b8, d0 [3] 28, 40, 58, 70, 88, a0, b8, d0 [4] 28, 40, 58, 70, 88, a0, b8, d0 [5] 28, 40, 58, 70, 88, a0, b8, d0 [6] 29, 41, 59, 71, 89, a1, b9, d1 [5:0] iareg iareg iareg iareg iareg iareg iereg 0 0 0 0 0 0 7h00 these are the per sts-12 alarm flags. tx mode of operation: other registers: 0 insert toh from serial ports 1 pass through all toh 0 insert toh from serial ports 1 pass through that particular toh byte the error insertion is based on a rising edge detector. as such the conrtol must be set to value 0 before trying to initiate a second a1 a2 corruption. the error insertion is based on a rising edge detector. as such the conrtol must be set to value 0 before trying to initiate a second b1 corruption. 0 do not insert error 1 insert error for number of frames in register hex 0c 0 do not insert error 1 insert error for 1 frame in b1 bits defined by register hex 0f
50 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 11. memory map descriptions (continued) bit/register name(s) bit/register location (hex) register type reset value (hex) description ais interrupt flags 12, 9, 6, 3 ais interrupt flags 11, 8, 5, 2, 10, 7, 4, 1 enable/mask register 12, 9, 6, 3 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 2a,42,5a,72, 8a, a2, ba, d2 [3:0] 2b,43,5b,73, 8b, a3, bb, d3 [7:0] 2c,44,5c,74, 8c, a4, bc, d4 [3:0] 2d,45,5d,75, 8d, a5, bd, d5 [7:0] iareg iareg iereg iereg 4h0 8h00 4h0 8h00 these are the ais-p alarm flags. es overflow flags 12, 9, 6, 3 es overflow flags 11, 8, 5, 2, 10, 7, 4, 1 enable/mask register 12, 9, 6, 3 enable/mask register 11, 8, 5, 2, 10, 7, 4, 1 2e,46,5e,76, 8e, a6, be, d6 [3:0] 2f,47,5f,77, 8f, a7, bf, d7 [7:0] 30,48,60,78, 90, a8, b0, d8 [3:0] 31,49,61,79, 91, a9, b1, d9 [7:0] iareg iareg iereg iereg 4h0 8h00 4h0 8h00 these are the elastic store overflow alarm flags. lvds link b1 parity error counter 32,4a,62,7a, 92, aa, b2, da [7:0] counter 8h00 7 bit count + overflow - reset on read lof counter 33,4b,63,7b, 93, ab, b3, db [7:0] counter 8h00 7 bit count + overflow - reset on read a1 a2 frame error counter 34,4c,64,7c, 94, ac, b4, dc [7:0] counter 8h00 7 bit count + overflow - reset on read fifo depth register 35, 4d, 65, 7d, 95, ad, c5, dd [4:0] sreg 0x0c 0x0c indicates fifo is half full. sampler phase error counter 36, 4e, 66, 7e, 96, ae, c6, de [7:0] counter 0x00 write 1 to clear bypass register 37,4f,67,7f,97,af ,c7,df[0] creg 0x0 1 - bypass pointer mover bypass register 37,4f,67,7f,97,af ,c7,df[1] creg 0x0 1 - bypass only alignment fifo + pointer mover enable work/protect channels 37,4f,67,7f,97,af ,c7,df[2] creg 0x0 bit to control the lvds drivers/receivers to/from cdr 0 - use lvds drivers and receivers to/from pi-sched i/f block b (work channels) 1 - use lvds drivers and receivers to/from pi-sched i/f block c (protect channels) sync control register 37,4f,67,7f,97,af ,c7,df[4:3] creg 2b00 00 - no alignment 01 - align with twin (i.e stm b stream a) 10 - align with all 4 (i.e. stm a all streams) 11 - align with all 8 (i.e. stm a and b all streams) disable framer 37,4f,67,7f,97,af ,c7,df[5] creg 0x0 0 - enable framer 1 - disable sts-12 framing cdr control register 1 0xe0[6] creg 0x0 enables cdr test mode. initiates cdrs built-in self test 0 - regular mode 1 - test mode 0xe0[5] creg 0x0 enables bypassing of the 622 mhz clock synthesis with tstclk 0 - use pll 1 - bypass pll 0xe0[4] creg 0x0 enables lvds loopback. 0 - no loopback 1 - loopback 0xe0[3] creg 0x0 when set to 1, controls bypass of 16 pll generated phases with 16 low-speed phases. 0xe0[2] creg 0x0 sets low speed internal interface frequency between macrocell and asics 1 = 212 mhz 0 = 106 mhz
lucent technologies inc. 51 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc memory map (continued) table 11. memory map descriptions (continued) bit/register name(s) bit/register location (hex) register type reset value (hex) description 0xe0[1] creg 0x0 en10bit. sets 10 to 1 mux/demux 1 = 10:1 mux/demux 0 = 8:1 mux/demux 0xe0[0] creg 0x0 0 = long-haul i/f mode (enables cdr + stm operation) 1 = short-haul i/f mode (disables cdr, enables pi-sched interfaces) cdr control register 2 0xe1[7:0] creg 0x0 sets input bit rate per channel 1 = 424 mbits/s 0 = 848 mbits/s cdr control register 3 0xe2[7:0] creg 0x0 sets input bit rate per channel (quartrate) 1 = 212 mbits/s 0 = 848 mbits/s cdr control register 4 0xe3[7:0] creg 0x0 enables 10 bit ethernet word alignment per channel pi-sched i/f ctl register 0xf0[1] creg used during internal built-in-self-test mode. 0 - no loopback 1 - loopback 0xf0[2] creg 0x0 reserved bit. (read-only) 0 - shuts down bidi logic and ignores auxiliary bypass signals. always set to 0 0xf0[7:3]] creg indicates minimum cell size and will be used to detect cell underrun errors. pi-sched i/f status register 0xf1[6] sreg indicates completion of the internal test. only valid when otestenb (0xf2[7] is high). 0 - test running 1 - test complete 0xf1[7] sreg indicates success of the internal test. valid only when itestdone is high 0 - test failed 1 - test passed pi-sched i/f ctl register 0xf2[6] creg 0x0 enables bypass of the pll circuit. tstclk is used in this mode. 0xf2[7] creg 0x0 1 - enables internal self test of the shim block. both internal and external loopback paths exist during this test. pll ctl register 0xf3[0] creg 0x0 pll testing control signal (see description on pg 88) 0xf3[1] creg 0x0 0xf3[7:2] creg 0x0
52 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc absolute maximum ratin g s stresses in excess of the absolute maximum ratin g s can cause permanent dama g e to the device. these are abso- lute stress ratin g s onl y . functional operation of the device is not implied at these or an y other conditions in excess of those g iven in the operations sections of this data sheet. exposure to absolute maximum ratin g s for extended periods can adversel y affect device reliabilit y . the orca series 3+ fpscs include circuitr y desi g ned to protect the chips from dama g in g substrate in j ection cur- rents and to prevent accumulations of static char g e. nevertheless, conventional precautions should be observed durin g stora g e, handlin g , and use to avoid exposure to excessive electrical stress. table 12 . absolute maximum ratin g s recommend o p eratin g conditions table 13 . recommend o p eratin g conditions parameter symbol min max unit stora g e temperature t st g C65 150 c power suppl y volta g e with respect to ground v dd 3 4.2 v v dd 15 2 v input si g nal with respect to ground v ss C 0.3 v ddio + 0.3 v si g nal applied to hi g h-impedance output v ss C 0.3 v ddio + 0.3 v maximum packa g e bod y temperature 220 c parameter symbol min max unit power suppl y volta g e with respect to ground v dd 32.7 3.6 v v dd 15 1.4 1.6 v input volta g es v in v ss C0.3 v ddio + 0.3 v junction temperature t j C40 125 c
lucent technologies inc. 53 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc hsi circuit specifications power supply decoupling lc circuit the 850 mhz hsi macro contains both analog and digital circuitry. the data recovery function, for example, is implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop to provide its 850 mhz reference frequency. the internal analog phase-locked loop contains a voltage-controlled oscillator. this circuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic gates and parasitic inductive elements. generated noise that contains frequency components beyond the band- width of the internal phase-locked loop (about 3 mhz) will not be attenuated by the phase-locked loop and will impact bit error rate directly. thus, separate power supply pins are provided for these critical analog circuit ele- ments. additional power supply filtering in the form of a lc pi filter section will be used between the power supply source and these device pins as shown in figure 15. the corner frequency of the lc filter is chosen based on the power supply switching frequency, which is between 100 khz and 300 khz in most applications. capacitors c1 and c2 are large electrolytic capacitors to provide the basic cutoff frequency of the lc filter. for example, the cutoff frequency of the combination of these elements might fall between 5 khz and 50 khz. capaci- tor c3 is a smaller ceramic capacitor designed to provide a low-impedance path for a wide range of high-frequency signals at the analog power supply pins of the device. the physical location of capacitor c3 must be as close to the device lead as possible. multiple instances of capacitors c3 can be used if necessary. the recommended filter for the hsi macro is shown below: l = 4.7 m h, rl = 1 w , c1 = 0.01 m f, c2 = 0.01 m f, c3 = 4.7 m f. 5-9344(f) figure 15. sample power supply filter network for analog hsi power supply pins c2 + c3 + to device pll_vdda pll_vssa c1 + from power supply source l
54 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc hsi electrical and timing characteristics table 14. absolute maximum ratings table 15. recommended operating conditions table 16. receiver specifications * scrambled data stream conforming to sonet sts-12 and sdh stm-4 data format using either a pn7 or pn9 sequence. n pn7 characteristic is 1 + x 6 + x 7 n pn9 characteristic is 1 + x 4 + x 9 ? this sequence should not occur more than once per minute. ? translates to a frequency change of 500 ppm. a unit interval for 622.08 mbits/s data is 1.6075 ns. table 17. transmitter specifications table 18.synthesizer specifications * (tbd) external 10 k w resistor to analog ground required. ? translates to a frequnecy change of 500 ppm. parameter conditions min typ max unti power dissipation 8 channels 300 mw parameter conditions min typ max unti v dd 15 supply voltage 1.4 1.6 v parameter conditions min typ max unti input data * stream of nontransitions ? 60bits phase change, input signal over a 200 ns time interval ? 100ps eye opening 0.4u ip-p jitter tolerance jitter tolerance: 250 khz 25 khz 2 khz 0.6 6 60 u ip-p u ip-p u ip-p parameter conditions min typ max unti output jitter, generated 250 khz to 5 mhz (measured with a spectrum analyzer) 0.15u ip-p output jitter, generated (inlcuding i/o buffers) 250 khz to 5 mhz 0.25 u ip-p parameter conditions min typ max unti pll * loop bandwidth 6 mhz jitter peaking 2 db powerup reset time 10 s lock aquisition time 1 ms input reference clock frequency 62.5 212.50 mhz frequency deviation 20 ppm phase change over a 200 ns time interval ? 100 ps
lucent technologies inc. 55 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc embedded core lvds i/o table 19. driver dc data* *v dd 33 = 3.1 v3.5 v, v dd 15 = 1.4 v1.6 v, C40 c, and slowfast process. ? external reference, ref10 = 1.0 v 3%, ref14 = 1.4 v 3% table 20. driver ac data * *v dd 33 = 3.1 v3.5 v, v dd 15 = 1.4 v1.6 v, C40 c, and slowfast process. table 21. driver power consumption * *v dd 33 = 3.1 v3.5 v, v dd 15 = 1.4 v1.6 v, C40 c, and slowfast process. parameter s y mbol test conditions min t yp max unit output volta g e hi g h, v oa or v ob v oh r load = 100 w 1% 1.475 ? v output volta g e low, v oa or v ob v ol r load = 100 w 1% 0.925 ? v output differential volta g e ? v od ? r load = 100 w 1% 0.25 0.45 ? v output offset volta g ev os r load = 100 w 1% 1.125* 1.275 ? v output impedance, differential r o v cm = 1.0 v and 1.4 v 80 100 120 w r o mismatch between a and b d r o v cm = 1.0 v and 1.4 v 10 % chan g e in differential volta g e between complimentar y states ?d v od ? r load = 100 w 1% 25 mv chan g e in output offset volta g e between complimentar y states d v os r load = 100 w 1% 25 mv output current i sa, i sb driver shorted to gnd 24 ma output current i sab drivers shorted to g ether 12 ma power-off output leaka g e|ixa|, |ixb|v dd = 0 v v pad , v padn = 0 v2.5 v 10ma parameter s y mbol test conditions min t yp max unit v od fall time, 80% to 20% t f z l = 100 w 1% c pad = 3.0 pf, c pad = 3.0 pf 100 210 ps v od rise time, 20% to 80% t r z l = 100 w 1% c pad = 3.0 pf, c pad = 3.0 pf 100 210 ps differential skew |t phla C t plhb | or |t phlb C t plha | t skew1 an y differential pair on packa g e at 50% point of the transition 50ps channel-to-channel skew |tpdiffm C tpdiffn|, t skew2 an y two si g nals on packa g e at 0 v dif- ferential ps propa g ation dela y time t plh t phl z l = 100 w 1% c pad = 3.0 pf, c padn = 3.0 pf 0.54 0.55 0.77 0.76 1.10 1.09 ns ns parameter s y mbol test conditions min max unit driver dc power pd dc z l = 100 w 1% 26.0 mw driver ac power pd ac z l = 100 w 1% c pad = 3.0 pf, c padn = 3.0 pf 64 m w/ mhz
56 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc embedded core lvds i/o (continued) lvds receiver buffer requirements table 22. receiver ac data * *v dd = 3.1 v3.5 v, 0 c 125 c , slow-fast process. table 23. receiver power consumption * *v dd = 3.1 v3.5 v, 0 c 125 c , slow-fast process. table 24. receiver dc data * *v dd = 3.1 v3.5 v, 0 c 125 c , slow-fast process. table 25. lvds operating parameters note: under worst-case operating condition, the lvds driver will withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. similarly, when outputs are short-circuited to each other or to ground, the lvds will not suffer permanent damage. the lvds driver supports hot-insertion. under a well-controlled environment, the lvds i/o can drive backplane as well as cable. parameter s y mbol test conditions min max unit pulse width distortion t pwd v idth = 100 mv, 450 mhz 160 ps propa g ation dela y time t plh t phl c l = 0.5 pf 0.60 0.60 1.41 1.47 ns ns with common-mode variation ( 0 v to 2.4 v ) ?d t pd ? c l = 0.5 pf 50 ps output rise time, 20% to 80% t r c l = 0.5 pf 150 350 ps output fall time, 80% to 20% t f c l = 0.5 pf 150 350 ps parameter s y mbol test conditions min max unit receiver dc power p rdc dc 20.4 mw receiver ac power p rac ac c l = 0.5 pf 4.5 m w/ mhz parameter s y mbol test conditions min t yp max unit input volta g e ran g e, via or vib v i ? v gpd ? < 925 mv dc C 1 mhz 0.0 1.2 2.4 v input differential threshold v idth ? v gpd ? < 925 mv 450 mhz C100 100 mv input differential h y steresis v hyst ( +v idthh ) C ( Cv idthl ) ? mv receiver differential input impedance r in with build-in termination, cen- ter-tapped 80 100 120 w parameter test conditions min normal max unit transmit termination resistor 80 100 120 w receiver termination resistor 80 100 120 w temperature ran g e C40 125 c power suppl y v dd 33 3.1 3.5 v power suppl y v dd 15 1.4 1.6 v power suppl y v ss 0v
lucent technologies inc. 57 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc in p ut/out p ut buffer measurement conditions ( on-lvds buffer ) note: switch to v dd for t plz /t pzl ; switch to gnd for t phz /t pzh . 5-3234(f) figure 16. ac test loads 5-3233.a(f) figure 17. output buffer delays 5-3235(f) figure 18. input buffer delays 50 pf a. load used to measure propagation delay to the output under test to the output under test 50 pf v cc gnd 1 k w b. load used to measure rising/falling edges v dd t phh v dd /2 v ss out[i] pad out 1.5 v 0.0 v t pll pad out[i] ac test loads ( shown above ) ts[i] out 0.0 v 1.5 v t phh t pll pad in[i] in 3.0 v v ss v dd /2 v dd pad in in[i]
58 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc lvds buffer characteristics termination resistor the lvds drivers and receivers operate on a 100 w differential impedance, as shown below. external resistors are not required. the differential driver and receiver buffers include termination resistors inside the device package as shown in figure 19 below. 5-8703(f) figure 19. lvds driver and receiver and associated internal components lvds driver buffer capabilities under worst-case operating condition, the lvds driver must withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. similarly, when its outputs are short-circuited to each other or to ground, the lvds driver will not suffer permanent damage. figure 20 illustrates the terms associated with lvds driver and receiver pairs. 5-8704(f) figure 20. lvds driver and receiver 5-8705(f) figure 21. lvds driver lvds driver 50 w 50 w lvds receiver center tap device pins 100 w external v gpd v oa v ob v ia v ib a b aa bb driver interconnect receiver v oa a v ob b c a c b r load v od = ( v oa C v ob ) v
lucent technologies inc. 59 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information this section describes the pins and signals that perform fpga-related functions. during configuration, the user- programmable i/os are 3-stated and pulled-up with an internal resistor. if any fpga function pin is not used (or not bonded to package pin), it is also 3-stated and pulled-up after configuration. table 26 . fpga common-function pin description symbol i/o description dedicated pins v dd 33 3 v positive power supply. v dd 15 1.5 v positive power supply for internal logic. v ddio positive power supply used by i/o banks. gnd ground supply. pll_vf dedicated pins for pll filtering. ptemp i temperature sensing diode pin. dedicated input. reset i during configuration, reset forces the restart of configuration and a pull-up is enabled. after configuration, reset can be used as a general fpga input or as a direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk i o in the master and asynchronous peripheral modes, cclk is an output which strobes con- figuration data in. in the slave or readback after configuration, cclk is input synchronous with the data on din or d[7:0]. cclk is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. done i as an input, a low level on done delays fpga start-up after configuration.* o as an active-high, open-drain output, a high level on this signal indicates that configura- tion is complete. done has an optional pull-up resistor. prgm i prgm is an active-low input that forces the restart of configuration and resets the bound- ary-scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during configuration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after configuration, rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the configuration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides configura- tion data out. if used in boundary-scan, tdo is test data out. cfg_irq /mpi_irq o during jtag, slave, master, and asynchronous peripheral configuration assertion on this cfg_irq (active-low) indicates an error or errors for block ram or fpsc initialization. mpi active-low interrupt request output. * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all user i/os) is controlled by a second set of options.
60 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information (continued) table 26. fpga common-function pin description (continued) symbol i/o description special-purpose pins (can also be used as a general i/o.) m[3:0] i during powerup and initialization, m0m3 are used to select the configuration mode with their values latched on the rising edge of init . during configuration, a pull-up is enabled. i/o after configuration, these pins are user-programmable i/o.* pll_ck[0:7] i/o dedicated pcm clock pins. these pins are a user-programmable i/o pins if not used by plls. p[tbtr]clk[1:0][ tc] i/o pins dedicated for the primary clock. input pins on the middle of each side with differential pairing. they may be used as general i/o pins if not needed for clocking purposes. tdi, tck, tms i if boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary-scan is not selected, all boundary-scan functions are inhibited once configuration is complete. even if boundary-scan is not used, either tck or tms must be held at logic 1 during configuration. each pin has a pull-up enabled during configuration. i/o after configuration, these pins are user-programmable i/o.* rdy/busy /rclk o during configuration in peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in asynchronous peripheral mode. after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.* i/o during the master parallel configuration mode, rclk is a read output signal to an external memory. this output is not normally used. hdc o high during configuration is output high until configuration is complete. it is used as a con- trol output, indicating that configuration is not complete. i/o after configuration, this pin is a user-programmable i/o pin.* ldc o low during configuration is output low until configuration is complete. it is used as a control output, indicating that configuration is not complete. i/o after configuration, this pin is a user-programmable i/o pin.* init i/o init is a bidirectional signal before and during configuration. during configuration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of configuration. after configuration, this pin is a user-programmable i/o pin.* cs0 , cs1 i cs0 and cs1 are used in the asynchronous peripheral, slave parallel, and microprocessor configuration modes. the fpga is selected when cs0 is low and cs1 is high. during con- figuration, a pull-up is enabled. i/o after configuration, these pins are user-programmable i/o pins.* rd /mpi_strb ird is used in the asynchronous peripheral configuration mode. a low on rd changes d7 into a status output. as a status indication, a high indicates ready, and a low indicates busy. wr and rd should not be used simultaneously. if they are, the write strobe overrides. this pin is also used as the mpi data transfer strobe. i/o after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.* * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration p ins (and the acti- vation of all user i/os) is controlled by a second set of options.
lucent technologies inc. 61 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information (continued) table 26. fpga common-function pin description (continued) symbol i/o description a[17:0] mpi_burst mpi_bdip mpi_tsz[1:0] a[21:0] i during mpi mode, the a[17:0] are used as the address bus driven by the powerpc bus master utilizing the least significant bits of the powerpc 32-bit address. o during master parallel configuration mode, a[17:0] address the configuration eprom. in mpi mode, many of the a[n] pins have alternate uses as described below. see the special function blocks section for more mpi information. during configuration, if not in master par- allel or an mpi configuration mode, these pins are 3-stated with a pull-up enabled. a[21] is used as the mpi_burst . it is driven low to indicate a burst transfer is in progress. driven high indicates that the current transfer is not a burst. a[22] is used as the mpi_bdip . it is driven by the powerpc processor assertion of this pin indicates that the second beat in front of the current one is requested by the master. negated before the burst transfer ends to abort the burst data phase. a[19:18] are used as the mpi_tsz[1:0] signals and are driven by the bus master to indicate the data transfer size for the transaction. set 01 for byte, 10 for half-word, and 00 for word. during master parallel mode a[21:0], address the configuration eproms up to 4m bytes. if not used for mpi, these pins are user-programmable i/o pins.* mpi_ack oin powerpc mode mpi operation, this is driven low indicating the mpi received the data on the write cycle or returned data on a read cycle. mpi_clk i this is the powerpc synchronous, positive-edge bus clock used for the mpi interface. it can be a source of the clock for the embedded system bus. if mpi is used, this can be the amba bus clock. mpi_tea o a low on the mpi transfer error acknowledge indicates that the mpi detects a bus error on the internal system bus for the current transaction. mpi_rtry o this pin requests the mpc860 to relinquish the bus and retry the cycle. d[31:0] i/o selectable data bus width from 8-, 16-, 32-bit. driven by the bus master in a write transac- tion. driven by mpi in a read transaction. i d[7:0] receive configuration data during master parallel, peripheral, and slave parallel con- figuration modes and each pin has a pull-up enabled. during serial configuration modes, d0 is the din input. d[7:3] output internal status for asynchronous peripheral mode when rd is low. after configuration, the pins are user-programmable i/o pins.* dp[3:0] i/o selectable parity bus width from 1, 2, 4-bit, dp[0] for d[7:0], dp[1] for d[15:8], dp[2] for d[23:16], and dp[3] for d[32:24]. after configuration, this pin is a user-programmable i/o pin.* din i during slave serial or master serial configuration modes, din accepts serial configuration data synchronous with cclk. during parallel configuration modes, din is the d0 input. during configuration, a pull-up is enabled. i/o after configuration, this pin is a user-programmable i/o pin.* dout o during configuration, dout is the serial data output that can drive the din of daisy-chained slave devices. data out on dout changes on the rising edge of cclk. i/o after configuration, dout is a user-programmable i/o pin.* * the fpga states of operation section contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration p ins (and the acti- vation of all user i/os) is controlled by a second set of options.
62 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information (continued) this section describes device i/o signals to/from the embedded core excluding the signals at the cic boundary. table 27. fpsc function pin description s y mbol i/o descri p tion hsi lvds pins rxd_b_p0 i lvds work linkchannel aa ( shared with rapidio ports b and c ) . rxd_b_n0 i lvds work linkchannel aa ( shared with rapidio ports b and c ) . rxd_c_p0 i lvds protect linkchannel aa ( shared with rapidio ports b and c ) . rxd_c_n0 i lvds protect linkchannel aa ( shared with rapidio ports b and c ) . rxd_b_p1 i lvds work linkchannel ab ( shared with rapidio ports b and c ) . rxd_b_n1 i lvds work linkchannel ab ( shared with rapidio ports b and c ) . rxd_c_p1 i lvds protect linkchannel ab ( shared with rapidio ports b and c ) . rxd_c_n1 i lvds protect linkchannel ab ( shared with rapidio ports b and c ) . rxd_b_p2 i lvds work linkchannel ac ( shared with rapidio ports b and c ) . rxd_b_n2 i lvds work linkchannel ac ( shared with rapidio ports b and c ) . rxd_c_p2 i lvds protect linkchannel ac ( shared with rapidio ports b and c ) . rxd_c_n2 i lvds protect linkchannel ac ( shared with rapidio ports b and c ) . rxd_b_p3 i lvds work linkchannel ad ( shared with rapidio ports b and c ) . rxd_b_n3 i lvds work linkchannel ad ( shared with rapidio ports b and c ) . rxd_c_p3 i lvds protect linkchannel ad ( shared with rapidio ports b and c ) . rxd_c_n3 i lvds protect linkchannel ad ( shared with rapidio ports b and c ) . rxd_b_p4 i lvds work linkchannel ba ( shared with rapidio ports b and c ) . rxd_b_n4 i lvds work linkchannel ba ( shared with rapidio ports b and c ) . rxd_c_p4 i lvds protect linkchannel ba ( shared with rapidio ports b and c ) . rxd_c_n4 i lvds protect linkchannel ba ( shared with rapidio ports b and c ) . rxd_b_p5 i lvds work linkchannel bb ( shared with rapidio ports b and c ) . rxd_b_n5 i lvds work linkchannel bb ( shared with rapidio ports b and c ) . rxd_c_p5 i lvds protect linkchannel bb ( shared with rapidio ports b and c ) . rxd_c_n5 i lvds protect linkchannel bb ( shared with rapidio ports b and c ) . rxd_b_p6 i lvds work linkchannel bc ( shared with rapidio ports b and c ) . rxd_b_n6 i lvds work linkchannel bc ( shared with rapidio ports b and c ) . rxd_c_p6 i lvds protect linkchannel bc ( shared with rapidio ports b and c ) . rxd_c_n6 i lvds protect linkchannel bc ( shared with rapidio ports b and c ) . rxd_b_p7 i lvds work linkchannel bd ( shared with rapidio ports b and c ) . rxd_b_n7 i lvds work linkchannel bd ( shared with rapidio ports b and c ) . rxd_c_p7 i lvds protect linkchannel bd ( shared with rapidio ports b and c ) . rxd_c_n7 i lvds protect linkchannel bd ( shared with rapidio ports b and c ) . pll_v dd a pll analo g v dd ( 3.3 v 5% ( shared with rapidio ports b and c )) . pll_v ss a pll analo g v ss ( gnd ) ( shared with rapidio ports b and c ) .
lucent technologies inc. 63 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information (continued) table 27. fpsc function pin description (continued) * bscan pins-tdi, tdo, tck, and tms are on fpga side. s y mbol i/o descri p tion hsi test si g nals tstclk i test clock for emulation of 622 mhz clock durin g pll b y pass. internal pull-down. mreset i test mode reset. internal pull-down. testrst i resets receiver clock division counter. internal pull-up. resettx i resets transmitter clock division counter. internal pull-up. tstmux [ 9:0 ] s o test mode output port. ra p idio lvds interface pins ( receiver ) rxd_a_p<7:0> i lvds data for rapidio , receiver port a. rxd_a_n<7:0> i lvds data for rapidio , receiver port a. rxsoc_a_p i lvds start-of-cell for rapidio , receiver port a. rxsoc_a_n i lvds start-of-cell for rapidio , receiver port a. rxclk_a_p i lvds receive clock for rapidio , receiver port a. rxclk_a_n i lvds receive clock for rapidio , receiver port a. lvctap_a<1:0> lvds input center tap ( use 0.01 uf to gnd ) . lvref10_a lvds reference volta g e: 1.0 v 3%. lvref14_a lvds reference volta g e: 1.4 v 3%. lvresh_a lvds resistor hi g h pin ( use 100 w to lvresl_a pin ) . lvresl_a lvds resistor low pin ( use 100 w to lvresh_a pin ) . rxd_b_p<7:0> i lvds data for rapidio , receiver port b. rxd_b_n<7:0> i lvds data for rapidio , receiver port b. rxsoc_b_p i lvds start-of-cell for rapidio , receiver port b. rxsoc_b_n i lvds start-of-cell for rapidio , receiver port b. rxclk_b_p i lvds receive clock for rapidio , receiver port b. rxclk_b_n i lvds receive clock for rapidio , receiver port b. lvctap_b<4:0> lvds input center tap ( use 0.01 uf to gnd ) . lvref10_b lvds reference volta g e: 1.0 v 3%. lvref14_b lvds reference volta g e: 1.4 v 3%. lvresh_b lvds resistor hi g h pin ( use 100 w to lvresl_b pin ) . lvresl_b lvds resistor low pin ( use 100 w to lvresh_b pin ) . rxd_c_p<7:0> i lvds data for rapidio , receiver port c. rxd_c_n<7:0> i lvds data for rapidio , receiver port c. rxsoc_c_p i lvds start-of-cell for rapidio , receiver port c. rxsoc_c_n i lvds start-of-cell for rapidio , receiver port c. rxclk_c_p i lvds receive clock for rapidio , receiver port c. rxclk_c_n i lvds receive clock for rapidio , receiver port c. lvctap_c<4:0> lvds input center tap ( use 0.01 uf to gnd ) . lvref10_c lvds reference volta g e: 1.0 v 3%. lvref14_c lvds reference volta g e: 1.4 v 3%. lvresh_c lvds resistor hi g h pin ( use 100 w to lvresl_c pin ) . lvresl_c lvds resistor low pin ( use 100 w to lvresh_c pin ) .
64 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information ( continued ) table 27. fpsc function pin descri p tion (continued) s y mbol i/o descri p tion ra p idio lvds interface pins ( transmitter ) txd_a_p<7:0> o lvds data for rapidio , transmitter port a. txd_a_n<7:0> o lvds data for rapidio , transmitter port a. txsoc_a_p o lvds start-of-cell for rapidio , transmitter port a. txsoc_a_n o lvds start-of-cell for rapidio , transmitter port a. txclk_a_p o lvds receive clock for rapidio , transmitter port a. txclk_a_n o lvds receive clock for rapidio , transmitter port a. txd_b_p<7:0> o lvds data for rapidio , transmitter port b. txd_b_n<7:0> o lvds data for rapidio , transmitter port b. txsoc_b_p o lvds start-of-cell for rapidio , transmitter port b. txsoc_b_n o lvds start-of-cell for rapidio , transmitter port b. txclk_b_p o lvds receive clock for rapidio , transmitter port b. txclk_b_n o lvds receive clock for rapidio , transmitter port b. txd_c_p<7:0> o lvds data for rapidio , transmitter port c. txd_c_n<7:0> o lvds data for rapidio , transmitter port c. txsoc_c_p o lvds start-of-cell for rapidio , transmitter port c. txsoc_c_n o lvds start-of-cell for rapidio , transmitter port c. txclk_c_p o lvds receive clock for rapidio , transmitter port c. txclk_c_n o lvds receive clock for rapidio , transmitter port c. misc s y stem si g nals rst_n i reset the core onl y . the fpga lo g ic is not reset b y rst_n. internal pull-down allows chip to sta y in reset state when external driver loses power. s y s_clk_p i lvds s y stem clock ( 77.76 mhz ) , 50% dut y c y cle, also the reference clock of pll. s y s_clk_n i lvds s y stem clock ( 77.76 mhz ) , 50% dut y c y cle, also the reference clock of pll. g clk_p i lvds clock for rapidio pll. g clk_n i lvds clock for rapidio pll. dxp temperature sensin g diode ( anode + ) . dxn temperature sensin g diode ( cathode C ) .
lucent technologies inc. 65 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information ( continued ) in table 28, an input refers to a signal flowing into the fgpa logic (out of the embedded core) and an output refers to a signal flowing out of the fpga logic (into the embedded core). table 28. embedded core/fpga interface signal description pin name i/o descri p tion stm si g nals dinaa<7:0> o parallel bus of stm slice a, transmitter a. msb is bit 7. dinaa_par o parit y for stm slice a, transmitter a. dinaa_fp o frame pulse for stm slice a, transmitter a. dinab<7:0> o parallel bus of stm slice a, transmitter b. msb is bit 7. dinab_par o parit y for stm slice a, transmitter b. dinab_fp o frame pulse for stm slice a, transmitter b. dinac<7:0> o parallel bus of stm slice a, transmitter c. msb is bit 7. dinac_par o parit y for stm slice a, transmitter c. dinac_fp o frame pulse for stm slice a, transmitter c. dinad<7:0> o parallel bus of stm slice a, transmitter d. msb is bit 7. dinad_par o parit y for stm slice a, transmitter d. dinad_fp o frame pulse for stm slice a, transmitter d. dinba<7:0> o parallel bus of stm slice b, transmitter a. msb is bit 7. dinba_par o parit y for stm slice b, transmitter a. dinba_fp o frame pulse for stm slice b, transmitter a. dinbb<7:0> o parallel bus of stm slice b, transmitter b. msb is bit 7. dinbb_par o parit y for stm slice b, transmitter b. dinbb_fp o frame pulse for stm slice b, transmitter b. dinbc<7:0> o parallel bus of stm slice b, transmitter c. msb is bit 7. dinbc_par o parit y for stm slice b, transmitter c. dinbc_fp o frame pulse for stm slice b, transmitter c. dinbd<7:0> o parallel bus of stm slice b, transmitter d. msb is bit 7. dinbd_par o parit y for stm slice b, transmitter d. dinbd_fp o frame pulse for stm slice b, transmitter d. doutaa<7:0> i parallel bus of stm slice a, receiver a. msb is bit 7. doutaa_par i parit y for parallel bus of stm slice a, receiver a. doutaa_spe i spe si g nal for parallel bus of stm slice a, receiver a. doutaa_c1 j 1 i c1j1 si g nal for parallel bus of stm slice a, receiver a. doutaa_en i enable for parallel bus of stm slice a, receiver a. doutaa_fp i frame pulse for parallel bus of stm slice a, receiver a. doutab<7:0> i parallel bus of stm slice b, receiver a. msb is bit 7. doutab_par i parit y for parallel bus of stm slice a, receiver b. doutab_spe i spe si g nal for parallel bus of stm slice a, receiver b. doutab_c1 j 1 i c1j1 si g nal for parallel bus of stm slice a, receiver b. doutab_en i enable for parallel bus of stm slice a, receiver b. doutab_fp i frame pulse for parallel bus of stm slice a, receiver b.
66 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information ( continued ) table 28. embedded core/fpga interface si g nal descri p tion (continued) pin name i/o descri p tion stm si g nals ( continued ) doutac<7:0> i parallel bus of stm slice a, receiver c. msb is bit 7. doutac_par i parit y for parallel bus of stm slice a, receiver c. doutac_spe i spe si g nal for parallel bus of stm slice a, receiver c. doutac_c1 j 1 i c1j1 si g nal for parallel bus of stm slice a, receiver c. doutac_en i enable for parallel bus of stm slice a, receiver c. doutac_fp i frame pulse for parallel bus of stm slice a, receiver c. doutad<7:0> i parallel bus of stm slice a, receiver d. msb is bit 7. doutad_par i parit y for parallel bus of stm slice a, receiver d. doutad_spe i spe si g nal for parallel bus of stm slice a, receiver d. doutad_c1 j 1 i c1j1 si g nal for parallel bus of stm slice a, receiver d. doutad_en i enable for parallel bus of stm slice a, receiver d. doutad_fp i frame pulse for parallel bus of stm slice a, receiver d. doutba<7:0> i parallel bus of stm slice b, receiver a. msb is bit 7. doutba_par i parit y for parallel bus of stm slice b, receiver a. doutba_spe i spe si g nal for parallel bus of stm slice b, receiver a. doutba_c1 j 1 i c1j1 si g nal for parallel bus of stm slice b, receiver a. doutba_en i enable for parallel bus of stm slice b, receiver a. doutba_fp i frame pulse for parallel bus of stm slice b, receiver a. doutbb<7:0> i parallel bus of stm slice b, receiver b. msb is bit 7. doutbb_par i parit y for parallel bus of stm slice b, receiver b. doutbb_spe i spe si g nal for parallel bus of stm slice b, receiver b. doutbb_c1 j 1 i c1j1 si g nal for parallel bus of stm slice b, receiver b. doutbb_en i enable for parallel bus of stm slice b, receiver b. doutbb_fp i frame pulse for parallel bus of stm slice b, receiver a. doutbc<7:0> i parallel bus of stm slice b, receiver c. msb is bit 7. doutbc_par i parit y for parallel bus of stm slice b, receiver c. doutbc_spe i spe si g nal for parallel bus of stm slice b, receiver c. doutbc_c1 j 1 i c1j1 si g nal for parallel bus of stm slice b, receiver c. doutbc_en i enable for parallel bus of stm slice b, receiver c. doutbc_fp i frame pulse for parallel bus of stm slice b, receiver c. doutbd<7:0> i parallel bus of stm slice b, receiver d. msb is bit 7. doutbd_par i parit y for parallel bus of stm slice b, receiver d. doutbd_spe i spe si g nal for parallel bus of stm slice b, receiver d. doutbd_c1 j 1 i c1j1 si g nal for parallel bus of stm slice b, receiver d. doutbd_en i enable for parallel bus of stm slice b, receiver d. doutbd_fp i frame pulse for parallel bus of stm slice b, receiver d.
lucent technologies inc. 67 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information ( continued ) table 28. embedded core/fpga interface si g nal descri p tion (continued) pin name i/o descri p tion toh si g nals toh_clk o tx and rx toh serial links clock ( 25 mhz to 77.76 mhz ) . toh_inaa o toh serial link for stm slice a, transmitter a. toh_inab o toh serial link for stm slice a, transmitter b. toh_inac o toh serial link for stm slice a, transmitter c. toh_inad o toh serial link for stm slice a, transmitter d. toh_inba o toh serial link for stm slice b, transmitter a. toh_inbb o toh serial link for stm slice b, transmitter b. toh_inbc o toh serial link for stm slice b, transmitter c. toh_inbd o toh serial link for stm slice b, transmitter d. tx_toh_ck_en o tx toh serial link clock enable. toh_outaa i toh serial link for stm slice a, receiver a. toh_outab i toh serial link for stm slice a, receiver b. toh_outac i toh serial link for stm slice a, receiver c. toh_outad i toh serial link for stm slice a, receiver d. toh_outba i toh serial link for stm slice b, receiver a. toh_outbb i toh serial link for stm slice b, receiver b. toh_outbc i toh serial link for stm slice b, receiver c. toh_outbd i toh serial link for stm slice b, receiver d. rx_toh_ck_en i rx toh serial link clock enable. rx_toh_fp i rx toh serial link frame pulse. toh_ck_fp_en i a soft re g ister bit available to enable rx toh clock and frame pulse. toh_aa_en i rx toh enable, soft re g ister. and output of resistor channel aa enable and hi-z control of toh data output aa. toh_ab_en i rx toh enable, soft re g ister. and output of resistor channel ab enable and hi-z control of toh data output ab. toh_ac_en i rx toh enable, soft re g ister. and output of resistor channel ac enable and hi-z control of toh data output ac. toh_ad_en i rx toh enable, soft re g ister. and output of resistor channel ad enable and hi-z control of toh data output ad. toh_ba_en i rx toh enable, soft re g ister. and output of resistor channel ba enable and hi-z control of toh data output ba. toh_bb_en i rx toh enable, soft re g ister. and output of resistor channel bb enable and hi-z control of toh data output bb. toh_bc_en i rx toh enable, soft re g ister. and output of resistor channel bc enable and hi-z control of toh data output bc. toh_bd_en i rx toh enable, soft re g ister. and output of resistor channel bd enable and hi-z control of toh data output bd.
68 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information ( continued ) table 28. embedded core/fpga interface signal description (continued) pin name i/o descri p tion stm clock and control s y s_fp o s y stem frame pulse for transmitter section. line_fp o line frame pulse for receiver section. fp g a_s y sclk i s y stem clock ( 77.76 mhz ) . prot_switch_aa o protection switchin g control si g nal. prot_switch_ac o protection switchin g control si g nal. prot_switch_ba o protection switchin g control si g nal. prot_switch_bc o protection switchin g control si g nal. lvds_prot_aa o protection switchin g control si g nal. lvds_prot_ab o protection switchin g control si g nal. lvds_prot_ac o protection switchin g control si g nal. lvds_prot_ad o protection switchin g control si g nal. lvds_prot_ba o protection switchin g control si g nal. lvds_prot_bb o protection switchin g control si g nal. lvds_prot_bc o protection switchin g control si g nal. lvds_prot_bd o protection switchin g control si g nal. core_read y idurin g powerup and fpga confi g uration se q uence, the core_read y is held low. at the end of fpga confi g uration, the core_read y will be held low for six clock ( s y s_clk ) c y cles and then g o active-hi g h. fla g indicates that the embedded core is out of its reset state. cdr_clk_aa i 77.76 mhz recovered clock for stm slice a, channel a. cdr_clk_ab i 77.76 mhz recovered clock for stm slice a, channel b. cdr_clk_ac i 77.76 mhz recovered clock for stm slice a, channel c. cdr_clk_ad i 77.76 mhz recovered clock for stm slice a, channel d. cdr_clk_ba i 77.76 mhz recovered clock for stm slice b, channel a. cdr_clk_bb i 77.76 mhz recovered clock for stm slice b, channel b. cdr_clk_bc i 77.76 mhz recovered clock for stm slice b, channel c. cdr_clk_bd i 77.76 mhz recovered clock for stm slice b, channel d. 8b/10b mode si g nals tx_k_ctrl_aa o k control bit for stm slice a, channel a. tx_k_ctrl_ab o k control bit for stm slice a, channel b. tx_k_ctrl_ac o k control bit for stm slice a, channel c. tx_k_ctrl_ad o k control bit for stm slice a, channel d. tx_k_ctrl_ba o k control bit for stm slice b, channel a. tx_k_ctrl_bb o k control bit for stm slice b, channel b. tx_k_ctrl_bc o k control bit for stm slice b, channel c. tx_k_ctrl_bd o k control bit for stm slice b, channel d.
lucent technologies inc. 69 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information ( continued ) table 28. embedded core/fpga interface si g nal descri p tion (continued) pin name i/o descri p tion ra p idio si g nals ( channel a ) cs y senb_a o s y stem cell processin g enable. after reset is released, drive this si g nal hi g h when rapidio is read y to transmit cells. this si g nal should be active after all control si g nals into the rapidio are stable. rstn_rx_a o s y nchronous reset for all memor y elements clocked b y wrxclk_a_fpga ( derived from pll ) . utxd_a<31:0> o transmit data bus containin g 4 octets s y nchronized with the risin g ed g e of the 60-146 mhz wutxclk_fpga ( derived from pll ) is clocked into the transmit fifo within the rapidio . utxsoc_a o start of cell ori g inatin g with the core and s y nchronized with the risin g ed g e of wutxclk_fpga into the transmit fifo. indi- cates the first data word on txd_a bus includes the first octet of a new cell in bit positions <31:24>. rstn_utx_a o s y nchronous reset for all memor y elements in the wutxclk_fpga domain. utxtristn_a o output 3-state enable ( active-low ) . when active, the txd_a, txsoc_a, and txclk_a lvds drivers are tri-stated. y tristn_a o 3-state override for transmit outputs ( active-low ) . this si g nal is i g nored durin g reset, but takes priorit y over all tri-state control si g nals otherwise. zrxd_a<31:0> i 32-bit data from the receive module. the bus contains 4 octets and reflects data received via the hi g h speed rxd_a data bus. zrxsoc_a i indicates the presence of the 1st octet of a new cell within the 1st 32-bit data word on the rxd_a bus in bit positions <31:24>. zrxsocviol_a i indicates a minimum cell violation within the receive module. this si g nal will transition active hi g h coincident with rxsoc. this indicates that the new cell overran the previous cell and that the previous cell is in violation of the minimum cell size. zrxalnviol_a i indicates an ali g nment error. an active state si g nals rxsoc was captured on a ne g ative rxclk ed g e. this si g nal will sta y hi g h for a sin g le wrxclk_a_fpga c y cle coincident with rxsoc. zclkstat_a i indicates the loss or absence of a clock on the lvds clock ( rxclk ) . after the validation of the absence of the clock, this si g nal will sta y hi g h for the duration of the absence of the clock. wrxclk_a_fp g a i derived from hi g h-speed lvds clock rxclk ( = rxclk/2 ) . ra p idio si g nals ( channel b ) cs y senb_b o s y stem cell processin g enable. after reset is released, drive this si g nal hi g h when rapidio is read y to transmit cells. this si g nal should be active after all control si g nals into the rapidio are stable.
70 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information ( continued ) table 28. embedded core/fpga interface si g nal descri p tion (continued) pin name i/o descri p tion ra p idio si g nals ( channel b ) continued rstn_rx_b o s y nchronous reset for all memor y elements clocked b y wrxclk_b_fpga ( derived from pll ) . utxd_b<31:0> o transmit data bus containin g 4 octets s y nchronized with the risin g ed g e of the 60146 mhz wutxclk_fpga ( derived from pll ) is clocked into the transmit fifo within the rapidio . utxsoc_b o start of cell ori g inatin g with the core and s y nchronized with the risin g ed g e of wutxclk_fpga into the transmit fifo. indi- cates the first data word on txd_b bus includes the first octet of a new cell in bit positions <31:24>. rstn_utx_b o s y nchronous reset for all memor y elements in the wutxclk_fpga domain. utxtristn_b o output 3-state enable ( active-low ) . when active, the txd_b, txsoc_b, and txclk_b lvds drivers are tri-stated. y tristn_b o 3-state override for transmit outputs ( active-low ) . this si g nal is i g nored durin g reset, but takes priorit y over all tri-state control si g nals otherwise. zrxd_b<31:0> i 32-bit data from the receive module. the bus contains 4 octets and reflects data received via the hi g h speed rxd_b data bus. zrxsoc_b i indicates the presence of the 1st octet of a new cell within the 1st 32-bit data word on the rxd_b bus in bit positions <31:24>. zrxsocviol_b i indicates a minimum cell violation within the receive module. this si g nal will transition active hi g h coincident with rxsoc. this indicates that the new cell overran the previous cell and that the previous cell is in violation of the minimum cell size. zrxalnviol_b i indicates an ali g nment error. an active state si g nals rxsoc was captured on a ne g ative rxclk ed g e. this si g nal will sta y hi g h for a sin g le wrxclk_b_fpga c y cle coincident with rxsoc. zclkstat_b i indicates the loss or absence of a clock on the lvds clock ( rxclk ) . after the validation of the absence of the clock, this si g nal will sta y hi g h for the duration of the absence of the clock. wrxclk_b_fp g a i derived from hi g h-speed lvds clock rxclk ( = rxclk/2 ) . ra p idio si g nals ( channel c ) cs y senb_c o s y stem cell processin g enable. after reset is released, drive this si g nal hi g h when rapidio is read y to transmit cells. this si g nal should be active after all control si g nals into the rapidio are stable. rstn_rx_c o s y nchronous reset for all memor y elements clocked b y wrxclk_c_fpga ( derived from pll ) .
lucent technologies inc. 71 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information ( continued ) table 28. embedded core/fpga interface si g nal descri p tion (continued) pin name i/o descri p tion ra p idio si g nals ( channel c ) continued utxd_c<31:0> o transmit data bus containin g 4 octets s y nchronized with the risin g ed g e of the 60-146 mhz wutxclk_fpga ( derived from pll ) is clocked into the transmit fifo within the rapidio . utxsoc_c o start of cell ori g inatin g with the core and s y nchronized with the risin g ed g e of wutxclk_fpga into the transmit fifo. indi- cates the first data word on txd_c bus includes the first octet of a new cell in bit positions <31:24>. rstn_utx_c o s y nchronous reset for all memor y elements in the wutxclk_fpga domain. utxtristn_c o output 3-state enable ( active-low ) . when active, the txd_c, txsoc_c, and txclk_c lvds drivers are tri-stated. y tristn_c o 3-state override for transmit outputs ( active-low ) . this si g nal is i g nored durin g reset, but takes priorit y over all tri-state control si g nals otherwise. zrxd_c<31:0> i 32-bit data from the receive module. the bus contains 4 octets and reflects data received via the hi g h speed rxd_c data bus. zrxsoc_c i indicates the presence of the 1st octet of a new cell within the first 32-bit data word on the rxd_c bus in bit positions <31:24>. zrxsocviol_c i indicates a minimum cell violation within the receive module. this si g nal will transition active hi g h coincident with rxsoc. this indicates that the new cell overran the previous cell and that the previous cell is in violation of the minimum cell size. zrxalnviol_c i indicates an ali g nment error. an active state si g nals rxsoc was captured on a ne g ative rxclk ed g e. this si g nal will sta y hi g h for a sin g le wrxclk_c_fpga c y cle coincident with rxsoc. zclkstat_c i indicates the loss or absence of a clock on the lvds clock ( rxclk ) . after the validation of the absence of the clock, this si g nal will sta y hi g h for the duration of the absence of the clock. wrxclk_c_fp g a i derived from hi g h-speed lvds clock rxclk ( = rxclk/2 ) . ra p idio si g nals wutxclk_fp g a i one x core clock ( 60-146 mhz ) g enerated from an internal pll circuit. input data on utxd<31:0> and utxsco are s y n- chronous to this clock. the transmit fifo inputs are clocked b y this clock. the test interface module also runs off this clock. this clock is sent to the fpga lo g ic. halfclk_fp g a i 1/2 x main pll output clock. phase ali g ned with pfclk. nominal fre q uenc y ran g e is 30 mhz to 73 mhz. dut y c y cle spec is 47%/53%.
72 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information ( continued ) package pinouts table 29 provides the package pin and pin function for the ort8850h fpsc and packages. the bond pad name is identified in the pio nomeclature used in the orca foundry design editor. the bank column provides information as to which output voltage level bank the given pin is in. the group column provides information as to the group of pins the given pin is in. this is used to show which vref pin is used to provide the reference voltage for single- ended limited-swing i/os. if none of these buffer types (such as sstl, gtl, hstl) are used in a given group, then the vref pin is available as an i/o pin. when the number of fpga bond pads exceeds the number of package pins, bond pads are unused. when the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). when a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for the fpga. the tables provide no information on unused pads.
lucent technologies inc. 73 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc pin information (continued) table 29. ort8850h 680-pin pbgam pinout ball bank group ort8850-pad function pair* differential e4 tl v dd 33 f5 tl prd_data rd_data/tdo d2 tl preset reset e3 tl prd_cfg rd_cfg g5 tl pprgrm prgrm f4 tl 7 pl2d pll_ck0c l21c_d2 complement d1 tl 7 pl2c pll_ck0t l21t_d2 true e2 tl 7 pl3d l22c_d0 complement f3 tl 7 pl3c vref l22t_d0 true g4 tl 7 pl4d d5 l23c_d0 complement h5 tl 7 pl4c d6 l23t_d0 true e1 tl 8 pl5d l24c_d0 complement f2 tl 8 pl5c vref l24t_d0 true j5 tl 8 pl6d hdc l25c_d1 complement g3 tl 8 pl6c ldc l25t_d1 true h4 tl 8 pl7d l26c_d2 complement f1 tl 8 pl7c l26t_d2 true g2 tl 9 pl8d l27c_d0 complement h3 tl 9 pl8c d7 l27t_d0 true k5 tl 9 pl9d vref l28c_d0 complement j4 tl 9 pl9c a17 l28t_d0 true g1 tl 9 pl10d cs0 l29c_d3 complement l5 tl 9 pl10c cs1 l29t_d3 true h2 tl 10 pl11d l30c_d0 complement j3 tl 10 pl11c l30t_d0 true k4 tl 10 pl11a true h1 tl 10 pl12d init l31c_d0 complement j2 tl 10 pl12c dout l31t_d0 true k3 tl 10 pl13d vref l32c_d0 complement l4 tl 10 pl13c a16 l32t_d0 true m5 tl 10 pl13a true j1 cl 1 pl14d a15 l1c_d0 complement k2 cl 1 pl14c a14 l1t_d0 true m4 cl 1 pl15d l2c_d0 complement l3 cl 1 pl15c l2t_d0 true * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
74 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential k1 cl 1 pl16d vref l3c_d3 complement n5 cl 1 pl16c d4 l3t_d3 true l2 cl 2 pl17d l4c_d1 complement n4 cl 2 pl17c l4t_d1 true p5 cl 2 pl18d rdy/busy /rclk l5c_d2 complement m2 cl 2 pl18c vref l5t_d2 true m1 cl 2 pl19d a13 l6c_d2 complement p4 cl 2 pl19c a12 l6t_d2 true n2 cl 3 pl20d l7c_d0 complement p3 cl 3 pl20c l7t_d0 true r5 cl 3 pl20a true r4 cl 3 pl21d a11 l8c_d2 complement n1 cl 3 pl21c vref l8t_d2 true t5 cl 3 pl21a true p2 cl 3 pl22d l9c_a0 complement p1 cl 3 pl22c l9t_a0 true r2 cl 3 pl22a l10t_d1 true t4 cl 3 pl22b l10c_d1 complement u5 cl 4 pl23d rd /mpi_strb l11c_d3 complement r1 cl 4 pl23c vref l11t_d3 true t3 cl 4 pl23a l12t_d1 true v5 cl 4 pl23b l12c_d1 complement t2 cl 4 pl24d plck0c l13c_a0 complement t1 cl 4 pl24c plck0t l13t_a0 true u4 cl 4 pl24b l14c_a0 complement u3 cl 4 pl24a l14t_a0 true u2 cl 5 pl25d a10 l15c_a0 complement v2 cl 5 pl25c a9 l15t_a0 true v3 cl 5 pl25b l16c_a0 complement v4 cl 5 pl25a l16t_a0 true w5 cl 5 pl26d a8 l17c_a2 complement w2 cl 5 pl26c vref l17t_a2 true w3 cl 5 pl27d l18c_d1 complement y1 cl 5 pl27c l18t_d1 true w4 cl 5 pl27a true * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
lucent technologies inc. 75 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential y2 cl 6 pl28d plck1c l19c_d0 complement aa1 cl 6 pl28c plck1t l19t_d0 true aa2 cl 6 pl28a true y5 cl 6 pl29d vref l20c_d3 complement ab1 cl 6 pl29c a7 l20t_d3 true y4 cl 6 pl29a true aa5 cl 6 pl30d a6 l21c_a1 complement aa3 cl 6 pl30c a5 l21t_a1 true ab2 cl 7 pl31d complement aa4 cl 7 pl32d wr /mpi_rw l22c_d2 complement ac1 cl 7 pl32c vref l22t_d2 true ab5 cl 7 pl33d l23c_d2 complement ac2 cl 7 pl33c l23t_d2 true ab4 cl 8 pl34d a4 l23c_d0 complement ac5 cl 8 pl34c vref l23t_d0 true ad2 cl 8 pl35d a3 l23c_d0 complement ae1 cl 8 pl35c a2 l23t_d0 true ac4 cl 8 pl35a true ad3 cl 8 pl36d a1 l24c_d0 complement ae2 cl 8 pl36c a0 l24t_d0 true af1 cl 8 pl37d dp0 l25c_d2 complement ad4 cl 8 pl37c dp1 l25t_d2 true ad5 cl 8 pl37a true ae3 bl 1 pl38d d8 l1c_d0 complement af2 bl 1 pl38c vref l1t_d0 true ag1 bl 1 pl38a true ae4 bl 1 pl39d d9 l2c_d0 complement af3 bl 1 pl39c d10 l2t_d0 true ae5 bl 2 pl40d l3c_d1 complement ag2 bl 2 pl40c vref l3t_d1 true ah1 bl 2 pl41d l4c_d3 complement af5 bl 2 pl41c l4t_d3 true af4 bl 3 pl42d d11 l5c_d0 complement ag3 bl 3 pl42c d12 l5t_d0 true ah2 bl 3 pl43d l6c_d0 complement * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
76 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential aj1 bl 3 pl43c l6t_d0 true ag4 bl 3 pl44d vref l7c_a0 complement ag5 bl 3 pl44c d13 l7t_a0 true ah3 bl 4 pl44b complement aj2 bl 4 pl45d l8c_d2 complement ah5 bl 4 pl45c vref l8t_d2 true ak1 bl 4 pl45a true ah4 bl 4 pl46d complement aj3 bl 4 pl46a true ak2 bl 4 pl47d pll_ck7c l9c_d0 complement al1 bl 4 pl47c pll_ck7t l9t_d0 true aj5 bl 4 pl47b l10c_a0 complement aj4 bl 4 pl47a l10t_a0 true ak3 bl ptemp ptemp al2 bl lvds_r lvds_r ak4 bl v dd 33 ak6 bl v dd 33 al5 bl 5 pb2a dp2 l11t_d1 true an4 bl 5 pb2b l11c_d1 complement am5 bl 5 pb2c pll_ck6t l12t_d1 true ak7 bl 5 pb2d pll_ck6c l12c_d1 complement ap4 bl 5 pb3a true al6 bl 5 pb3c l13t_d1 true an5 bl 5 pb3d l13c_d1 complement am6 bl 5 pb4c vref l14t_d0 true al7 bl 5 pb4d dp3 l14c_d0 complement ak8 bl 6 pb5c l15t_d3 true ap5 bl 6 pb5d l15c_d3 complement ak9 bl 6 pb6c vref l16t_d2 true an6 bl 6 pb6d d14 l16c_d2 complement am7 bl 6 pb7c l17t_d1 true ap6 bl 6 pb7d l17c_d1 complement al8 bl 7 pb8c d15 l18t_d1 true an7 bl 7 pb8d d16 l18c_d1 complement ak10 bl 7 pb9a true * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
lucent technologies inc. 77 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential am8 bl 7 pb9c d17 l19t_d0 true al9 bl 7 pb9d d18 l19c_d0 complement ak11 bl 7 pb10a true ap7 bl 7 pb10c vref l20t_d0 true an8 bl 7 pb10d d19 l20c_d0 complement am9 bl 8 pb11a true al10 bl 8 pb11c d20 l21t_d2 true ap8 bl 8 pb11d d21 l21c_d2 complement an9 bl 8 pb12a true al11 bl 8 pb12c vref l22t_d0 true am10 bl 8 pb12d d22 l22c_d0 complement ak12 bl 9 pb13a l23t_d3 true ap9 bl 9 pb13b l23c_d3 complement an10 bl 9 pb13c d23 l24t_d1 true al12 bl 9 pb13d d24 l24c_d1 complement am11 bl 9 pb14a l25t_d1 true ap10 bl 9 pb14b l25c_d1 complement ak13 bl 9 pb14c vref l26t_d2 true an11 bl 9 pb14d d25 l26c_d2 complement al13 bl 9 pb15c l27t_d0 true ak14 bl 9 pb15d l27c_d0 complement an12 bl 10 pb16c d26 l28t_d1 true al14 bl 10 pb16d d27 l28c_d1 complement ap12 bl 10 pb17c l29t_d0 true an13 bl 10 pb17d l29c_d0 complement ap13 bl 10 pb18c vref l30t_d3 true ak15 bl 10 pb18d d28 l30c_d3 complement am14 bl 11 pb19a true al15 bl 11 pb19c d29 l31t_d0 true ak16 bl 11 pb19d d30 l31c_d0 complement an14 bl 11 pb20a true ap14 bl 11 pb20c vref l32t_d2 true al16 bl 11 pb20d d31 l32c_d2 complement an15 bc 1 pb21a true ap15 bc 1 pb21c l1t_d3 true * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
78 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential ak17 bc 1 pb21d l1c_d3 complement am16 bc 1 pb22a true an16 bc 1 pb22c vref l2t_d1 true al17 bc 1 pb22d l2c_d1 complement ap16 bc 2 pb23a l3t_d1 true am17 bc 2 pb23b l3c_d1 complement an17 bc 2 pb23c pbck0t l4t_d1 true al18 bc 2 pb23d pbck0c l4c_d1 complement am18 bc 2 pb24b l5c_a0 complement an18 bc 2 pb24a l5t_a0 true an19 bc 2 pb24c vref l6t_d2 true ak18 bc 2 pb24d l6c_d2 complement am19 bc 2 pb25c l7t_a0 true al19 bc 2 pb25d l7c_a0 complement ap20 bc 3 pb26c l8t_d3 true ak19 bc 3 pb26d vref l8c_d3 complement an20 bc 3 pb27a true ap21 bc 3 pb27c l9t_d2 true al20 bc 3 pb27d l9c_d2 complement ak20 bc 3 pb28a true an21 bc 3 pb28c pbck1t l10t_a0 true am21 bc 3 pb28d pbck1c l10c_a0 complement ak21 bc 3 pb29a true ap22 bc 4 pb29c l11t_d2 true al21 bc 4 pb29d l11c_d2 complement an22 bc 4 pb30a true ap23 bc 4 pb30c l12t_a0 true an23 bc 4 pb30d vref l12c_a0 complement ak22 bc 4 pb31c l13t_a0 true al22 bc 4 pb31d l13c_a0 complement an24 bc 5 pb32c l14t_d2 true ak23 bc 5 pb32d vref l14c_d2 complement al23 bc 5 pb33c l15t_d0 true am24 bc 5 pb33d l15c_d0 complement ap25 bc 5 pb34c l16t_a0 true * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
lucent technologies inc. 79 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential an25 bc 5 pb34d l16t_a0 complement ap26 bc 6 pb35a true ak25 bc 6 pb35c l17t_a0 true an26 bc 6 pb35d vref l17c_a0 complement ap27 bc 6 pb36a true am25 bc 6 pb36c l18t_d3 true ak26 bc 6 pb36d l18c_d3 complement al24 cr txd_c0_n l1n_a0 complement ak24 cr txd_c0_p l1p_a0 true an27 cr txd_c1_n l2n_d0 complement ap28 cr txd_c1_p l2p_d0 true al25 cr txd_c2_n l3n_a0 complement al26 cr txd_c2_p l3p_a0 true am26 cr txd_c3_n l4n_a0 complement am27 cr txd_c3_p l4p_a0 true an28 cr txsoc_c_n l5n_d0 complement ap29 cr txsoc_c_p l5p_d0 true al27 cr txclk_c_n l6n_a0 complement ak27 cr txclk_c_p l6p_a0 true al28 cr txd_c4_n l7n_a0 complement ak28 cr txd_c4_p l7p_a0 true am28 cr txd_c5_n l8n_d0 complement an29 cr txd_c5_p l8p_d0 true ak29 cr txd_c6_p l9p_a0 true al29 cr txd_c6_n l9n_a0 complement ap30 cr txd_c7_n l10n_d0 complement an30 cr txd_c7_p l10p_d0 true am29 cr dautrec ap31 cr tstclk am30 cr testrst an31 cr tstshftld al30 cr resettx ah30 cr etoggle aj30 cr ecsel al33 cr exdnup * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
80 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential ah31 cr mreset ak32 cr rxd_c0_n l11n_d0 complement aj31 cr rxd_c0_p l11p_d0 true al34 cr rxd_c1_n l12n_d0 complement ak33 cr rxd_c1_p l12p_d0 true aj32 cr lvctap_c_0 af30 cr rxd_c2_n l13n_a0 complement ag30 cr rxd_c2_p l13p_a0 true ag31 cr rxd_c3_n l14n_a0 complement af31 cr rxd_c3_p l14p_a0 true ak34 cr lvctap_c_1 aj33 cr rxsoc_c_n l15n_a0 complement ah32 cr rxsoc_c_p l15p_a0 true aj34 cr rxclk_c_n l16n_d0 complement ah33 cr rxclk_c_p l16p_d0 true ad30 cr lvctap_c_2 ag32 cr rxd_c4_n l17n_a0 complement ag33 cr rxd_c4_p l17p_a0 true ah34 cr lvctap_c_3 ae30 cr rxd_c5_n l18n_a0 complement ae31 cr rxd_c5_p l18p_a0 true af32 cr rxd_c6_n l19n_a0 complement af33 cr rxd_c6_p l19p_a0 true ac30 cr lvctap_c_4 ag34 cr rxd_c7_n l20n_a0 complement af34 cr rxd_c7_p l20p_a0 true ab30 cr v dd a_stm ad31 cr v ss a_stm ae32 cr sys_clk_n l21n_d0 complement ae33 cr sys_clk_p l21p_d0 true ae34 cr lvctap_sk ac31 cr rxd_b0_n l22n_a0 complement ab31 cr rxd_b0_p l22p_a0 true ad32 cr rxd_b1_n l23n_a0 complement ad33 cr rxd_b1_p l23p_a0 true * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
lucent technologies inc. 81 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential aa30 cr lvctap_b_0 ac33 cr rxd_b2_n l24n_a0 complement ac34 cr rxd_b2_p l24p_a0 true ab33 cr rxd_b3_n l25n_a0 complement ab34 cr rxd_b3_p l25p_a0 true y30 cr lvctap_b_1 aa31 cr rxsoc_b_n l26n_a0 complement aa32 cr rxsoc_b_p l26p_a0 true w30 cr rxclk_b_n l27n_d0 complement y31 cr rxclk_b_p l27p_d0 true aa33 cr lvctap_b_2 aa34 cr rxd_b4_n l28n_a0 complement y34 cr rxd_b4_p l28p_a0 true y33 cr lvctap_b_3 w31 cr rxd_b5_n l29n_a0 complement w32 cr rxd_b5_p l29p_a0 true v30 cr rxd_b6_n l30n_a0 complement v31 cr rxd_b6_p l30p_a0 true w33 cr lvctap_b_4 v32 cr rxd_b7_n l31n_a0 complement v33 cr rxd_b7_p l31p_a0 true u33 cr reslo u32 cr reshi u31 cr ref14 t33 cr ref10 t32 cr txd_b0_n l32n_d1 complement r34 cr txd_b0_p l32p_d1 true u30 cr txd_b1_n l33n_d0 complement t31 cr txd_b1_p l33p_d0 true r33 cr txd_b2_n l34n_d0 complement p34 cr txd_b2_p l34p_d0 true p33 cr txd_b3_n l35n_d0 complement n34 cr txd_b3_p l35p_d0 true t30 cr txsoc_b_n l36n_d0 complement r31 cr txsoc_b_p l36p_d0 true * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
82 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential p32 cr txclk_b_n l37n_d1 complement r30 cr txclk_b_p l37p_d1 true n33 cr txd_b4_n l38n_d0 complement m34 cr txd_b4_p l38p_d0 true p31 cr txd_b5_n l39n_d1 complement m33 cr txd_b5_p l39p_d1 true n31 cr txd_b6_n l40n_d0 complement p30 cr txd_b6_p l40p_d0 true l33 cr txd_b7_n l41n_d0 complement k34 cr txd_b7_p l41p_d0 true m31 cr gclk_n l42n_d0 complement l32 cr gclk_p l42p_d0 true k33 cr lvctap_gk n30 cr v dd a_shim l30 cr v ss a_shim m30 cr rxd_a0_n l43n_d0 complement l31 cr rxd_a0_p l43p_d0 true j34 cr rxd_a1_n l44n_d1 complement k32 cr rxd_a1_p l44p_d1 true h34 cr rxd_a2_n l45n_d1 complement j33 cr lvctap_a_0 j32 cr rxd_a2_p l45p_d1 true k30 cr rxd_a3_p l46p_a0 true k31 cr rxd_a3_n l46n_a0 complement h33 cr lvctap_a_1 j30 cr rxsoc_a_p l47p_a0 true j31 cr rxsoc_a_n l47n_a0 complement g34 cr rxclk_a_n l48n_d1 complement h32 cr rxclk_a_p l48p_d1 true h31 cr lvctap_a_2 g33 cr rxd_a4_n l49n_d0 complement f34 cr rxd_a4_p l49p_d0 true h30 cr lvctap_a_3 g32 cr rxd_a5_n l50n_d0 complement f33 cr rxd_a5_p l50p_d0 true * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
lucent technologies inc. 83 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential g30 cr rxd_a6_n l51n_a0 complement g31 cr rxd_a6_p l51p_a0 true e34 cr lvctap_a_4 f32 cr rxd_a7_n l52n_a0 complement e33 cr rxd_a7_p l52p_a0 true f31 cr tstmux0s e32 cr tstmux1s d34 cr tstmux2s d33 cr tstmux3s f30 cr tstmux4s d30 cr tstmux5s e29 cr tstmux6s c30 cr tstmux7s b31 cr tstmux8s d29 cr tstmux9s a31 cr scan_tstmd b30 cr scanen b29 cr rst e28 cr txd_a0_n l53n_d1 complement c29 cr txd_a0_p l53p_d1 true d28 cr txd_a1_n l54n_d0 complement e27 cr txd_a1_p l54p_d0 true a30 cr txd_a2_n l55n_d1 complement c28 cr txd_a2_p l55p_d1 true b28 cr txd_a3_n l56n_d0 complement a29 cr txd_a3_p l56p_d0 true d27 cr txsoc_a_n l57n_d0 complement e26 cr txsoc_a_p l57p_d0 true c27 cr txclk_a_n l58n_d0 complement d26 cr txclk_a_p l58p_d0 true a28 cr txd_a4_n l59n_d0 complement b27 cr txd_a4_p l59p_d0 true c26 cr txd_a5_n l60n_d0 complement d25 cr txd_a5_p l60p_d0 true a27 cr txd_a6_n l61n_d0 complement * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
84 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential b26 cr txd_a6_p l61p_d0 true d24 cr txd_a7_n l62n_d0 complement c25 cr txd_a7_p l62p_d0 true a26 tc 1 pt35d l1c_d3 complement e25 tc 1 pt35c l1t_d3 true b25 tc 1 pt35a l2t_a0 true a25 tc 1 pt35b l2c_a0 complement c24 tc 1 pt34d vref l3c_d0 complement d23 tc 1 pt34c l3t_d0 true b24 tc 1 pt33d l4c_a2 complement e24 tc 1 pt33c l4t_a2 true d22 tc 2 pt32d l5c_d1 complement b23 tc 2 pt32c vref l5t_d1 true e23 tc 2 pt31d l6c_a3 complement a23 tc 2 pt31c l6t_a3 true d21 tc 2 pt30d l7c_d1 complement b22 tc 2 pt30c l7t_d1 true a22 tc 3 pt29d l8c_d1 complement c21 tc 3 pt29c vref l8t_d1 true e22 tc 3 pt29a true d20 tc 3 pt28d l9c_d1 complement b21 tc 3 pt28c l9t_d1 true e21 tc 3 pt28a true a21 tc 3 pt27d l10c_d0 complement b20 tc 3 pt27c l10t_d0 true a20 tc 3 pt27a true e20 tc 4 pt26d l11c_d0 complement d19 tc 4 pt26c l11t_d0 true c19 tc 4 pt25d l12c_a0 complement b19 tc 4 pt25c l12t_a0 true e19 tc 4 pt24d l13c_d0 complement d18 tc 4 pt24c vref l13t_d0 true c18 tc 4 pt24a l14t_a0 true b18 tc 4 pt24b l14c_a0 complement b17 tc 5 pt23d ptck1c l15c_a0 complement * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
lucent technologies inc. 85 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential c17 tc 5 pt23c ptck1t l15t_a0 true d17 tc 5 pt23a l16t_d2 true a16 tc 5 pt23b l16c_d2 complement b16 tc 5 pt22d ptck0c l17c_a0 complement c16 tc 5 pt22c ptck0t l17t_a0 true d16 tc 5 pt22a true e18 tc 5 pt21d vref l18c_d3 complement a15 tc 5 pt21c l18t_d3 true b15 tc 5 pt21a true d15 tc 6 pt20d l19c_d2 complement a14 tc 6 pt20c l19t_d2 true b14 tc 6 pt20a true e17 tc 6 pt19d l20c_d2 complement c14 tc 6 pt19c vref l20t_d2 true d14 tc 6 pt19a true e16 tl 1 pt18d mpi_rtry l1c_d3 complement a13 tl 1 pt18c mpi_ack l1t_d3 true b13 tl 1 pt17d l2c_d0 complement a12 tl 1 pt17c vref l2t_d0 true b12 tl 1 pt16d m0 l3c_d1 complement d13 tl 1 pt16c m1 l3t_d1 true e15 tl 2 pt15d mpi_clk l4c_d3 complement b11 tl 2 pt15c a21/mpi_burst l4t_d3 true a10 tl 2 pt14d m2 l5c_d3 complement e14 tl 2 pt14c m3 l5t_d3 true d12 tl 2 pt13d vref l6c_d0 complement c11 tl 2 pt13c mpi_tea l6t_d0 true b10 tl 3 pt12d l7c_d0 complement a9 tl 3 pt12c l7t_d0 true d11 tl 3 pt12a true c10 tl 3 pt11d vref l8c_d0 complement b9 tl 3 pt11c l8t_d0 true e13 tl 3 pt11a true a8 tl 3 pt10d d0 l9c_d2 complement d10 tl 3 pt10c tms l9t_d2 true * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
86 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential c9 tl 4 pt9d a20/mpi_bdip l10c_d0 complement b8 tl 4 pt9c a19/mpi_tsz1 l10t_d0 true a7 tl 4 pt8d a18/mpi_tsz0 l11c_d4 complement e12 tl 4 pt8c d3 l11t_d4 true d9 tl 4 pt7d vref l12c_d0 complement c8 tl 4 pt7c l12t_d0 true e11 tl 5 pt6d d1 l13c_d3 complement b7 tl 5 pt6c d2 l13t_d3 true a6 tl 5 pt5d l14c_d2 complement d8 tl 5 pt5c vref l14t_d2 true c7 tl 5 pt4d tdi l15c_d1 complement a5 tl 5 pt4c tck l15t_d1 true e10 tl 5 pt4b l16c_d2 complement d7 tl 5 pt4a l16t_d2 true a4 tl 6 pt3d l17c_d4 complement e9 tl 6 pt3c vref l17t_d4 true b6 tl 6 pt3b l18c_a0 complement c6 tl 6 pt3a l18t_a0 true b5 tl 6 pt2d pll_ck1c l19c_d1 complement d6 tl 6 pt2c pll_ck1t l19t_d1 true c5 tl 6 pt2b l20c_d0 complement e8 tl -- pcfg_mpi_irq cfg_irq /mpi_irq b4 tl 6 pt2a l20t_d0 true e7 tl -- pcclk cclk d5 tl -- pdone done e6 tl -- v dd 33 a1 tl -- v ss a2 tl v ss a18 tl v ss a33 tl v ss a34 tl v ss b1 tl v ss b2 tl v ss b33 tl v ss b34 tl v ss * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
lucent technologies inc. 87 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential c3 tl v ss c13 tl v ss c22 tc v ss c32 tc v ss d4 tc v ss d31 tc v ss n3 tc v ss n13 tc v ss n14 tc v ss n15 tc v ss n20 tc v ss n21 tc v ss n22 tc v ss n32 cr v ss p13 cr v ss p14 cr v ss p15 cr v ss p20 cr v ss p21 cr v ss p22 cr v ss r13 cr v ss r14 cr v ss r15 cr v ss r20 cr v ss r21 cr v ss r22 cr v ss t16 cr v ss t17 cr v ss t18 cr v ss t19 cr v ss t34 cr v ss u16 cr v ss u17 cr v ss u18 cr v ss u19 cr v ss * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
88 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential v1 cr v ss v16 cr v ss v17 cr v ss v18 cr v ss v19 cr v ss v34 cr v ss w16 cr v ss w17 cr v ss w18 cr v ss w19 cr v ss y13 cr v ss y14 cr v ss y15 bc v ss y20 bc v ss y21 bc v ss y22 bc v ss aa13 bc v ss aa14 bc v ss aa15 bc v ss aa20 bc v ss aa21 bc v ss aa22 bc v ss ab3 bc v ss ab13 bl v ss ab14 bl v ss ab15 bl v ss ab20 bl v ss ab21 bl v ss ab22 bl v ss ab32 bl v ss al4 bl v ss al31 bl v ss am3 bl v ss am13 bl v ss am22 cl v ss * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
lucent technologies inc. 89 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential am32 cl v ss an1 cl v ss an2 cl v ss an33 cl v ss an34 cl v ss ap1 cl v ss ap2 cl v ss ap18 cl v ss ap33 cl v ss ap34 cl v ss n16 tl v dd 15 n17 tl v dd 15 n18 tl v dd 15 n19 tl v dd 15 p16 tl v dd 15 p17 tc v dd 15 p18 tc v dd 15 p19 tc v dd 15 r16 tc v dd 15 r17 tc v dd 15 r18 cr v dd 15 r19 cr v dd 15 t13 cr v dd 15 t14 cr v dd 15 t15 cr v dd 15 t20 cr v dd 15 t21 cr v dd 15 t22 cr v dd 15 u13 cr v dd 15 u14 cr v dd 15 u15 cr v dd 15 u20 cr v dd 15 u21 cr v dd 15 u22 cr v dd 15 v13 cr v dd 15 * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
90 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential v14 cr v dd 15 v15 cr v dd 15 v20 cr v dd 15 v21 cr v dd 15 v22 cr v dd 15 w13 cr v dd 15 w14 cr v dd 15 w15 cr v dd 15 w20 bc v dd 15 w21 bc v dd 15 w22 bc v dd 15 y16 bc v dd 15 y17 bc v dd 15 y18 bl v dd 15 y19 bl v dd 15 aa16 bl v dd 15 aa17 bl v dd 15 aa18 bl v dd 15 aa19 cl v dd 15 ab16 cl v dd 15 ab17 cl v dd 15 ab18 cl v dd 15 ab19 cl v dd 15 a3 tl v dd io_tl b3 tl v dd io_tl c1 tl v dd io_tl c2 tl v dd io_tl c4 tl v dd io_tl d3 tl v dd io_tl e5 tl v dd io_tl a11 tc v dd io_tc a17 tc v dd io_tc a19 tc v dd io_tc a24 tc v dd io_tc c12 tc v dd io_tc * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
lucent technologies inc. 91 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc ball bank group ort8850-pad function pair* differential c15 tc v dd io_tc c20 tc v dd io_tc c23 tc v dd io_tc a32 cr v dd 33 b32 cr v dd 33 c31 cr v dd 33 c33 cr v dd 33 c34 cr v dd 33 d32 cr v dd 33 e30 cr v dd 33 e31 cr v dd 33 l34 cr v dd 33 m32 cr v dd 33 r32 cr v dd 33 u34 cr v dd 33 w34 cr v dd 33 y32 cr v dd 33 ac32 cr v dd 33 ad34 cr v dd 33 ak30 cr v dd 33 ak31 cr v dd 33 al32 cr v dd 33 am31 cr v dd 33 am33 cr v dd 33 am34 cr v dd 33 an32 cr v dd 33 ap32 cr v dd 33 am12 bc v dd io_bc am15 bc v dd io_bc am20 bc v dd io_bc am23 bc v dd io_bc ap11 bc v dd io_bc ap17 bc v dd io_bc ap19 bc v dd io_bc ap24 bc v dd io_bc pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued) * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball.
92 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc * differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is ninteenth pair in an associated bank ). the c indi- cates complementary differential whereas a t indicates true differential. the _a0 indicates the physical location is adjacent b alls in either hor- zontal/vertical direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates diagonally adjacent separated by one physical ball. ball bank group ort8850-pad function pair* differential ak5 bl v dd io_bl al3 bl v dd io_bl am1 bl v dd io_bl am2 bl v dd io_bl am4 bl v dd io_bl an3 bl v dd io_bl ap3 bl v dd io_bl l1 cl v dd io_cl m3 cl v dd io_cl r3 cl v dd io_cl u1 cl v dd io_cl w1 cl v dd io_cl y3 cl v dd io_cl ac3 cl v dd io_cl ad1 cl v dd io_cl pin information (continued) table 29. ort8850h 680-pin pbgam pinout (continued)
lucent technologies inc. 93 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc packa g e thermal characteristics summar y there are three thermal parameters that are in com- mon use: q ja , y jc, and q jc . it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. q ja this is the thermal resistance from junction to ambient (theta-ja, r-theta, etc.). where t j is the junction temperature, t a, is the ambient air temperature, and q is the chip power. experimentally, q ja is determined when a special ther- mal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced convection measurements. a controlled amount of power (q) is dissipated in the test chips heater resistor, the chips temperature (t j ) is deter- mined by the forward drop on the diodes, and the ambi- ent temperature (t a ) is noted. note that q ja is expressed in units of c/watt. y jc this jedec designated parameter correlates the junc- tion temperature to the case temperature. it is generally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance, and it is defined by: where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. during the q ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. y jc is also expressed in units of c/w. q jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is defined by: the parameters in this equation have been defined above. however, the measurements are performed with the case of the part pressed against a water-cooled heat sink to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates q jc from y jc. q jc is a true thermal resistance and is expressed in units of c/w. q jb this is the thermal resistance from junction to board ( q jl ). it is defined by: where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other param- eters on the right-hand side have been defined above. this is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. note that q jb is expressed in units of c/w, and that this parameter and the way it is mea- sured are still in jedec committee. fpsc maximum junction temperature once the power dissipated by the fpsc has been determined (see the estimating power dissipation sec- tion), the maximum junction temperature of the fpsc can be found. this is needed to determine if speed der- ating of the device from the 85 c junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in c), the max- imum junction temperature is approximated by: t jmax = t amax + (q ? q ja ) ta b l e 3 0 lists the thermal characteristics for all pack- ages used with the orca ort8850 series of fpscs. q ja t j t a C q ------------------- - = y jc t j t c C q -------------------- = q jc t j t c C q -------------------- = q jb t j t b C q ------------------- - =
94 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc packa g e thermal characteristics table 30 . orca ort8850 plastic package thermal guidelines packa g e co p lanarit y the coplanarity limits of the lucent packages are as follows: n pbgam: 8.0 mils packa g e parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 31 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capacitance of the lead to the near- est neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. resistance values are in m w. the parasitic values in table 31 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designers model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. table 31. orca ort8850 package parasitics 5-3862(c)r2 figure 22. package parasitics packa g e q ja ( c/w ) t = 70 c max t j = 125 c max 0 f p m ( w ) 0 f p m200 f p m 500 f p m 680-pin pbgam 14.5 tbd tbd 3.8 packa g e t yp el sw l mw r w c 1 c 2 c m l sl l ml 680-pin pbgam 3.8 1.3 250 1.0 1.0 0.3 2.85 0.51 pad n l sw r w circuit board pad c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 l sl pad n + 1
lucent technologies inc. 95 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc packa g e outline dia g rams terms and definitions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for fit and tol- erance. typical (typ): when specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension.
96 lucent technologies inc. preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc package outline diagrams (continued) 680-pin pbgam dimensions are in millimeters. 5-4406(f) seating plane solder ball 0.50 0.10 0.20 35.00 t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab a 19 30 26 28 24 32 22 20 18 4 6 8 10121416 2 34 52325 731 29 15 21 327 11 17 913 1 33 33 spaces @ 1.00 = 33.00 33 spaces a1 ball 0.64 0.15 a1 ball @ 1.00 = 33.00 corner 30.00 1.170 + 0.70 C 0.00 35.00 30.00 + 0.70 C 0.00 identifier zone 2.51 max 0.61 0.08
lucent technologies inc. 97 preliminary data sheet september 2000 eight-channel x 850 mbits/s backplane transceiver orca ort 8850 fpsc hardware orderin g information 5-6435 (f) table 32. device type options table 33. temperature options table 34. package type options table 35 . orca fpsc package matrix (speed grades) software ordering information implementing a design in an ort8850h/l requires the orca foundry development system and an ort8850 fpsc desgin kit. for ordering information please visit: http://www.lucent.com/micro/netcom/ipkits/ort8850/ device parameter value ort8850l volta g e 1.5 v core 3.3 v/2.5 v i/o packa g e 680-pin pbgam 352-pin pbga. two channels with redundanc y onl y ort8850h volta g e 1.5 v core 3.3 v/2.5 v i/o packa g e 680-pin pbgam s y mbol descri p tion tem p erature ( blank ) commercial 0 c to 70 c i industrial C40 c to +85 c s y mbol descri p tion bm plastic ball grid arra y , multila y er ba plastic ball grid arra y device package 680-pin pbgam 352-pin pbga bm680 ba352 ort8850l C1, C2 C1, C2 ort8850h C1, C2 device type package type ort8850(l)(h) bm number of pins temperature range 680 -2 speed grade
lucent technologies inc. reserves the right to make changes to the product(s) or information contained herein without notice. n o liability is assumed as a result of their use or application. no rights under any patent accompany the sale of any such product(s) or information. orca is a registered trademark of lucent technologies inc. foundry is a trademark of xilinx copyright ? 2000 lucent technologies inc. all rights reserved printed in u.s.a. september 2000 ds00-406fpga for additional information, contact your microelectronics group account manager or the following: internet: http://www.lucent.com/micro , or for fpga information, http://www.lucent.com/orca e-mail: docmaster@micro.lucent.com n. america: microelectronics group, lucent technologies inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia pacific: microelectronics group, lucent technologies singapore pte. ltd., 77 science park drive, #03-18 cintech iii, singap ore 118256 tel. (65) 778 8833 , fax (65) 777 7495 china: microelectronics group, lucent technologies (china) co., ltd., a-f2, 23/f, zao fong universe building, 1800 zhong shan xi road, shanghai 200233 p. r. china tel. (86) 21 6440 0468 , ext. 325 , fax (86) 21 6440 0652 japan: microelectronics group, lucent technologies japan ltd., 7-18, higashi-gotanda 2-chome, shinagawa-ku, tokyo 141, japan tel. (81) 3 5421 1600 , fax (81) 3 5421 1700 europe: data requests: microelectronics group dataline: tel. (44) 7000 582 368 , fax (44) 1189 328 148 technical inquiries: germany: (49) 89 95086 0 (munich), united kingdom: (44) 1344 865 900 (ascot), france: (33) 1 40 83 68 00 (paris), sweden: (46) 8 594 607 00 (stockholm), finland: (358) 9 3507670 (helsinki), italy: (39) 02 6608131 (milan), spain: (34) 1 807 1441 (madrid)

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